Pranay Krishna Randhi — Software Engineer

Senior DFT Engineer with 4 yrs of experience in Spyglass to Post-silicon Design for Test (DFT) activities. I have hands on experience in Boundary Scan, MBIST, Scan insertion, EDT, ATPG (Automatic Test Pattern Generation) for Stuck-At and Transition faults. Also worked on Coverage Analysis and implementation of improvement techniques. My skills also include RTL & gate level Simulations (Both Timing & No Timing, PG and Non-PG) for ATPG patterns, BSCAN and MBIST patterns. Also, Part of successful Tape Out’s (BTO & MTO) supporting ECO’s required for VCLP checks and design related. Supported the Emulation (Veloce) team and ATE team for Silicon Diagnosis on Teradyne ultraFLEX using IG-XL software

Stackforce AI infers this person is a DFT Engineer specializing in VLSI and post-silicon testing.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs