Prashant Sankh

Software Engineer

Vijayapura, Karnataka, India1 yr 3 mos experience

Key Highlights

Experienced in ASIC Digital Design and VLSI.
Strong background in RTL coding and verification.
Passionate about public speaking and effective communication.

Stackforce AI infers this person is a VLSI Design Engineer with a focus on ASIC and digital design verification.

Contact

Skills

Core Skills

AsicDigital DesignVlsiVerificationRtl Design

Other Skills

Advanced VerilogLintRTL CodingUVMUniversal Verification Methodology (UVM)Electronic EngineeringDigital DesignsSystemVerilogCode CoverageVerilogLogic DesignDigital ElectronicsInterpersonal SkillsCommunicationAnalytical Skills

About

Having completed a Bachelor’s Degree in Electronics and Communication Engineering, I opted to equip myself with industry relevant skills in the rapidly growing realm of VLSI and kick-start my career in the same. Apart from what is known as academics, I also actively take part in Public Speaking, Seminars, Presentations and anything that includes effective communication. I would like to address myself as an Orator as I’m well spoken. Educating/Tutoring is what I enjoy the most. I also read novels and involve myself in singing. Brief enough :)

Experience

1 yr 3 mos

Total Experience

1 yr 3 mos

Average Tenure

1 yr 3 mos

Current Experience

Synopsys inc

2 roles

ASIC Digital Design Engineer

Mar 2025 – Present · 1 yr 3 mos · Hyderabad, Telangana, India · On-site

ASICDigital Design

Intern (Techincal-Engineering)

Aug 2024 – Mar 2025 · 7 mos · Hyderabad, Telangana, India · On-site

Maven silicon

VLSI Design and Verification Trainee

Jul 2023 – Feb 2024 · 7 mos · Bengaluru, Karnataka, India · On-site

I worked on a couple of industry standard projects which helped me gain hands on experience and also improved my coding and debugging skills.
1) Router 1x3 Design and Verification :
Studied the block level architecture and
specifications and implemented RTL code.
Developed UVM Testbench with multiple
test cases to verify the RTL.
2) SPI Master Core Verification :
Studied the protocol specifications and
features.
Developed UVM Testbench with different
testcases such as variable character length,
transmitting(Tx) and receiving(Rx)
the data at posedge and negedge of the
clock, data tranfer from MSB and LSB
and thus verified the SPI Master-Core.