P

Prateek Mishra

Product Engineer

Santa Clara, California, United States5 yrs experience
Highly Stable

Key Highlights

  • Expert in low power circuit design methodologies.
  • Hands-on experience in SRAM design at advanced technology nodes.
  • Proven ability to improve system performance metrics.
Stackforce AI infers this person is a Semiconductor and Electronics design expert with a focus on low power technologies.

Contact

LinkedIn

Skills

Core Skills

Circuit DesignCad MethodologiesSram DesignLow-power Design

Other Skills

Low power FinFET circuit designspatial variabilitytemporal variabilityanalysislayoutasynchronous designsynchronous systems

Experience

5 yrs
Total Experience
5 yrs
Average Tenure
--
Current Experience

Oracle corporation

Senior Hardware Design Engineer

Jan 2011 – Jan 2011 · 0 mo

Ibm t j watson

Student Intern

Jun 2008 – Aug 2008 · 2 mos

  • SRAM design, analysis and layout at the 22nm technology node
SRAM designanalysislayoutSRAM Design

Princeton university

Graduate Student

Sep 2006 – Oct 2011 · 5 yrs 1 mo

  • PhD Thesis -> Low power FinFET (3D transistor) circuit design and
  • associated CAD methodologies under spatial and temporal variability
Low power FinFET circuit designCAD methodologiesspatial variabilitytemporal variabilityCircuit DesignCAD Methodologies

Concordia university

Undergraduate Technical Intern

May 2005 – Jul 2005 · 2 mos

  • · Designed a low-power asynchronous wrapper that could communicate between two
  • synchronous systems with independent clocks
  • · Results showed better delay, throughput and power characteristics as compared to
  • previous designs in literature
Low-power designasynchronous designsynchronous systemsLow-power Design

Education

Princeton University

PhD — EECS

Jan 2006 – Jan 2010

Indian Institute of Technology, Kanpur

BTech — EE

Jan 2002 – Jan 2006

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