Radhe Shyam Gupta

Software Engineer

Delhi, India13 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in chip level synthesis and STA for automotive SoCs.
Led successful tapeout of IoT and Smartphone IPs.
Proficient in low-power design and timing closure.

Stackforce AI infers this person is a VLSI design engineer with expertise in automotive and IoT semiconductor industries.

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Skills

Core Skills

Static Timing AnalysisLow-power DesignSynthesisFpga

Other Skills

Constraints developmentPPA activitiesDesign cycle supportIntegration activitiesSTALECCLPConstraints checksECOsSub System Level STATop level STATiming sign-offECOConstraint cleanupMBIST Insertion

About

*Full ownership for chip level synthesis, sta and other integration activities of automotive SoCs *Full integration ownership for SoC partitions and blocks of Smartphone SoCs *Full ownership of block and subsys level integration activities for data center and networking chips *Full ownership for chip level and block level integration activities of IoT based projects *Sub System Level STA (Pre and Post Layout) *Top level STA (Post Layout) *7nm,12nm, 14nm finfet node *28nm cmos node *160nm cmos node for analog dominant IPs and chips *Block Level STA (Pre-layout and Post Layout) *Timing closure, X-Talk analysis, Signal Integrity Analysis, Timing ECO, Metal ECO *Prime-Time, Tweaker, Gold-Time, Tempus *Design Compiler, RTL Compiler, Genus *Conformal LEC *Conformal CLP *CPF based low power design *UPF writing and flow based generation *Synthesis (Block, subsystem and SoC level) *Memory BIST insertion *DFT, Scan Stitching *Isolation Cell Insertion, CDC, Power Domain Crossing *Leakage Power Recovery *FPGA Implementation

Experience

13 yrs 1 mo

Total Experience

1 yr 9 mos

Average Tenure

6 yrs 6 mos

Current Experience

Stmicroelectronics

3 roles

Sr Staff Engineer

Promoted

Apr 2025 – Present · 1 yr 2 mos

Working as Sr Staff Engineer.
Responsible for Constraints development for automotive microcontroller microcontrollers.
Responsible for PPA activities for platform and top, constraints verification and supporting throughout design cycle.

Constraints developmentPPA activitiesDesign cycle supportStatic Timing AnalysisLow-power Design

Staff Engineer

Apr 2022 – Mar 2025 · 2 yrs 11 mos

Technical Lead

Oct 2019 – Mar 2022 · 2 yrs 5 mos

Mediatek

2 roles

Senior Engineer

Jun 2018 – Sep 2019 · 1 yr 3 mos

Handled integration activities for Smartphone SoC partitions and Modems viz.
Synthesis, STA, LEC, CLP, Constraints and Clock Tree checks etc.

Integration activitiesSynthesisSTALECCLPConstraints checks+1

Engineer (STA & Synthesis)

Dec 2016 – May 2018 · 1 yr 5 mos

Worked on multiple smartphone and IoT projects:
Integration activities at SoC level smartphone projects
Full ownership of IoT based projects
Lead a small team to accomplish successful tapeout of IoT and Smartphone IPs
Lead a small team to successfully achieve different milestones of Smartphone SoC partition.
Activities: Synthesis, LEC, CLP, ERC, STA, Functional and Timing ECOs, Pad pin assignment

Integration activitiesSynthesisLECCLPECOsStatic Timing Analysis

Qualcomm

STA Engineer (As a consultant through Aricent)

Aug 2016 – Dec 2016 · 4 mos · Bangalore

Worked as a consultant through Aricent techology.
Sub System Level STA (Pre and Post layout) for central tile of a mobile SOC
Top level STA (Pre and Post layout)
Timing sign-off
ECO (Functional and timing)
Constraint cleanup feedback
Design issue feedback
Placement and routing quality feedback
FT Budgeting

Sub System Level STATop level STATiming sign-offECOConstraint cleanupStatic Timing Analysis

Aricent

2 roles

Design Implementation Engineer

Oct 2015 – Dec 2016 · 1 yr 2 mos

Block ownership for STA, Synthesis, MBIST Insertion, Scan Stitching, Low Power Checks, Timing sign-off and Leakage Power Recovery of multi million, multi power domain and multi clock blocks.

STASynthesisMBIST InsertionScan StitchingStatic Timing Analysis

Design Engineer Trainee

Mar 2015 – Sep 2015 · 6 mos

Worked with SmartPlay Technology PVT LTD (An Aricent Company) for PMC Sierra in Implementation Group, responsible for Synthesis, RAMBIST & DFT insertion, LEC, CLP, Power Gating, Prelayout & Postlayout STA of block level and subsystem level designs.
Trained on Synthesis through GDS-II flow and basic Standard Cell Library Design and Characterization using Synopsys and Cadence Tools with the help of SmartPlay experts, PMC experts, Global University of Engineering and Seer Akademy.

SynthesisDFT insertionLECPower Gating

Pmc-sierra

Integration Engineer (As a consultant through Aricent)

Jun 2015 – May 2016 · 11 mos · Bangalore

Worked as consultant through Aricent/Smartplay Responsible for Synthesis, Formal Verification, DFT Stitching, RAMBIST Insertion and Timing Closure (STA)

SynthesisFormal VerificationDFT StitchingTiming Closure

Indian institute of information technology

Teaching Assistnat

Jul 2012 – Jun 2014 · 1 yr 11 mos · Greater Allahabad Area

Project guidance based on FPGA and Micro-controllers, ASIC and FPGA implementation with Verilog using VCS, PrimeTime, DC compiler, Precision RTL, QuestaSim, Xilinx ISE.
Taught Microprocessor architecture and interfacing and conducted labs for undergraduate and postgraduate students

FPGA implementationASIC implementationVerilogFPGA