Jan 2021 – Jul 2022 · 1 yr 6 mos

• Development, RTL Compiler, VELOCE
• Working extensively in leading a team of three members on various RTL design enhancement and optimization projects, some of them including FSM Coverage, Mixed Design Configuration, Design Hierarchy Optimization, etc. involving interaction with multiple teams in parallel and focusing on delivering high quality and timely product releases.
• Responsibility of tracking and analysis of customer design issues and accordingly assigning to appropriate members of the team so as to provide effective solutions.
• Active participation in giving tech talks within the organization and maintaining regular discussions within the team thereby driving continuous product improvement and innovation.

Aug 2017 – Dec 2020 · 3 yrs 4 mos

• Development, RTL Compiler, VELOCE
• With experience, got an opportunity to work on other phases of logic synthesis process like RTL design elaboration and partitioning while handling support of RTL constructs.
• Worked on identifying bottle necks in the existing code support and performing optimizations so as to reduce design compile time.
• Independent responsibility in design, development and support of various complex customer features such as requiring class design from scratch, preparing HLD, LLD and user level documents, mentoring other individuals and peer code review.
• Experience of working on customer design issues, interacting with customer and responding them with solutions in crunch situations.
• Accreditation: Got Spot bonus award for exceptional performance in feature development.

Oct 2015 – Aug 2017 · 1 yr 10 mos

• Development, RTL Compiler, VELOCE
• As a starter in EDA domain, got an opportunity to learn Verilog and VHDL languages, end to end logic synthesis process and comparison of results with other simulation or synthesis tools.
• Got an opportunity to work primarily on Control and Data Flow Graph (CDFG) and netlist creation phase of logic synthesis process while taking care of development and support of logic synthesis of various Verilog and System Verilog constructs.
• Experience of end to end understanding of the existing code flow and taking care of minute implementation details so as to perform efficient coding and testing while extending the code support for some enhancements or bug fixes.

Jul 2014 – Oct 2015 · 1 yr 3 mos · Hyderabad Area, India

• Development, LTE Small Cells
• Worked on SON (Self Optimizing Networks) development in LTE Small cells team.
• Primarily responsible for development and support of Transmit Power Management (TPM) feature for LTE small cells and integrating it with full LTE stack.
• Handling of bug fixes for some of the important features of SON and Radio Resource Management (RRM) modules.
• Exposure to software tools and languages like C++, GDB, GIT in Linux environment.
• Accreditation: Got Qualstar award for best team performance in Qualcomm.

Jun 2013 – May 2014 · 11 mos · Kharagpur Area, India

• User Authentication Using Keyboard Dynamics
• Improvement of existing security system which presently uses only login detail to authenticate the user.
• Built a system using machine learning models which is capable of continuously authenticating the user using keyboard dynamics during their entire active login period.
• Integration of keyboard dynamics with other biometrics like mouse and face and developed a working software prototype of the same.

Dec 2010 – Dec 2011 · 1 yr · Pune Area, India

• Oracle Transportation Management
• Completed initial fresher training of 3 months covering all the important computer science subjects.
• Post training, joined OTM team and was responsible for understanding the basic functionalities of the OTM tool, capturing of customer requirements and customer business scenarios and thereafter customization of the tool based on the customer business.