Rajat Saxena

Software Engineer

Delhi, India7 yrs 11 mos experience
Highly Stable

Key Highlights

  • Senior Lead Engineer with extensive SoC DV experience.
  • Proficient in ASIC design and functional verification.
  • Hands-on experience with multiple digital design projects.
Stackforce AI infers this person is a Digital Design Engineer with expertise in ASIC and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationApplication-specific Integrated Circuits (asic)VerilogSystem Verilog

Other Skills

Test PlanningDebuggingDigital ElectronicsStatic Timing AnalysisVHDLC (Programming Language)C++Universal Verification Methodology (UVM)Python (Programming Language)QuestasimXilinx ISEModel SimLinuxBash ScriptingTcl-Tk

Experience

7 yrs 11 mos
Total Experience
2 yrs 5 mos
Average Tenure
10 mos
Current Experience

Qualcomm

Senior Lead Engineer

Aug 2025 – Present · 10 mos · Noida, Uttar Pradesh, India · On-site

Test PlanningDebuggingFunctional VerificationDigital ElectronicsVerilogSystem Verilog+17

Nxp semiconductors

Lead Design Engineer

Mar 2022 – Sep 2025 · 3 yrs 6 mos · Noida, Uttar Pradesh, India

Functional VerificationApplication-Specific Integrated Circuits (ASIC)

Synopsys inc

2 roles

Applications Engineer II

Dec 2020 – Apr 2022 · 1 yr 4 mos

Applications Engineer I

Jan 2019 – Dec 2020 · 1 yr 11 mos

3st technologies

Engineer trainee

Jul 2018 – Jan 2019 · 6 mos · Noida, Uttar Pradesh, India

  • Learnt verilog,system verilog,UVM,VHDL,c,c++,perl,tcl/tk etc.work on industry level projects such as UART,I2C,digital alarm clock,counter sv environment, adder SV environment, FIFO SV environment etc.
VerilogSystem VerilogUVMVHDLCC+++2

Education

Ambedkar Institute of Advanced Communication Technologies and Research

Bachelor of Technology

Jan 2014 – Jan 2018

rajkiya pratibha vikas vidyalaya lajpat nagar

senior secondary — science

Jan 2012 – Jan 2014

Stackforce found 100+ more professionals with Functional Verification & Application-specific Integrated Circuits (asic)

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