Rakesh Misra

Director of Engineering

Bengaluru, Karnataka, India25 yrs 5 mos experience

Highly Stable

Key Highlights

Director of Engineering with extensive SoC architecture experience.
Awarded multiple patents and recognition awards for innovation.
Proven track record in leading cross-functional engineering teams.

Stackforce AI infers this person is a Wireless Industry Expert specializing in SoC architecture and microarchitecture.

Contact

Skills

Core Skills

MicroarchitectureDesignPower Management

Other Skills

Power architecturePythonARM ArchitectureLow Power DesignVHDLTechnical Project LeadershipProject EngineeringSystems EngineeringPython (Programming Language)Engineering ManagementGate Level SimulationComputer LiteracyRTL DevelopmentDigital IC DesignDigital Designs

About

Experienced Engineering Manager with a demonstrated history of working in the wireless industry. Strong engineering professional skilled in ARM CPU architectures, RISC-V CPU microarchitectures, Hardware(SoC) Architecture, Converged coherent fabric microarchitecture, Client/Server Power architecture ,RTL Coding, RTL/gate level verification, Joint Test Action Group (JTAG), Emulation, Software debug & firmware development and validation.

Experience

25 yrs 5 mos

Total Experience

6 yrs 7 mos

Average Tenure

6 yrs 6 mos

Current Experience

Intel corporation

Director Of Engineering

Dec 2019 – Present · 6 yrs 6 mos · Bangalore India

CPU tech leader/Director, SoC power architect involved across many cross functional teams with main responsibilities of understanding product, architectural requirements and providing technical feedbacks on design/PPA optimizations, Uarch development, generating design reference docs. Reviews of RTL & Testplans. Reviews & QC of functional/timing/power ecos ,debugs.
 xPU (GPU+CPU) SoC Uarch understanding and development, proposals to next gen xPU products.
 Converged Coherent Fabric IP development -> Uarch, IDI protocols, Cache coherency protocols – MSI/MESI/MOESI/MESIF/MOESIF used across Client segments &Servers .
Generated : configsXfrequenciesXnodes(N3/N6/10/10+++), scalable to generate non-supported configurations with all types of xactions.
ADLN Client (laptop segment) : Power arch ,Uarch delivered SoC Power MAS ( Client SP)
Detailed Visio of SoC Pwr rail mapping, Platform->SoC->Partition->HIP/SIP pwr conn.
PG pin (HIP/AIP/SIP) conn checker & MPG<-MINI-<-PGIRTRIM checker (ADLN Vs K0/L0/R0) per partition.
Written algorithm and re-usable tool in Python for automated power rail connectivity visio generation and pwr conn checking against BE UPFs.
BUMP Sort Die-file/Pkg/PnP/BI/TIU,Vrails map package balls->pkg bumps->die bumps-> logic for ICC MAX per rail (Vnom),BI ICCMAX (BI )
Generated pwr up sequences, Boot ,PKG C*/S* states given to SW teams. HVM/BI/TIU teams for tests and content development.
Client (laptop SoC) : Uarch reviews of multicore CPU sub-system involving four cluster quad Cortex A53 ,Boot, GIC, Timers, CPR, DTS .Int strategies. Pwr rail definitions, debug sub-system design. Reviewed all design aspects, DFD infrastructure. Testplans , testcases. debugs.
Filed IDF that received Patent, Distinguished Invention Award ( Method and Apparatus of identify and validate highly critical non-resettable flops in the boot path in a Closed Chassis Sys) 24th May 2022.
Received 15 recognition awards from cross-functional teams .

DesignMicroarchitecture

Qualcomm

Principal Engineer/Manager

Nov 2004 – Dec 2019 · 15 yrs 1 mo · Bangalore

Employed by QUALCOMM India Pvt. (“QIPL”) from 18th Nov 2004 ,Serving as Principal Engineer/Manager with 5 awarded US patents.Successful tape out of nearly 35 CPU sub-systems , proven in silicon.
Awarded Super Qualstars in 2013 and 2015 for successful commercialization (from design to customer phones) of high end snapdragon products (8x20 ,8x35)
Awarded 22 Qualstars for tremendous contribution to design/verification/emulation/software and customer debug supports.
With 19+ years of experience my responsibility in India include , but are not limited to the following :
Requirement analysis of ARM based sub-system architectures.
Hardware design and ownership of Multicore Cortex-A57/A53/A73/A75 based sub-systems
Low power architecture, components development and analysis.
RISCV processor architecture, micro architecture development.
Hardware design, RTL coding of sub-system interfaces like protocol converters, debug logic and low power controller logic.
Good understanding of ARM V7,V8, V8.2 architecture.
CPU Type (LITTLE Cluster, big Cluster ) A75/A73/A72/A55A53/A57/ Coherent interconnects CCI400/CCI500/CCI550
Boot support from Boot FSM without involving external small CPU like RPM
Split vs shared power rail architecture.
DCVS with interconnect counters
L2/L3 HS ,clock gating for L1 I/D and L2 tag rams to save dynamic power.
Design to support memory periphery HS removal ,gaining 7-9% access time. HW Counters for LPM mode entry/exit
Per Core Dynamic Retention and L2 dynamic retention,Power manager advanced fall through and power manager assisted L2 flush,Di/Dt DCVS/WFx mitigation
Voltage/temp/current/CPR sensors management,Buck Peak Current Limit Management
JTAG/APB based scan dumps to dump state.
Address, interrupt, security & fuse map definitions
Frequency plan & Memory specification generation
Design/DV/Post silicon reviews
Software support and FW development