Ram Kumar Gajula — Software Engineer
∴ Overall 5+ years of experience in VLSI domain. ∴ Experienced in ASIC Physical design with strong knowledge on CMOS, Digital Electronics & Physical design concepts. ∴ Experience on 5nm, 6nm, 7nm, 14nm, 28nm, 65nm & 90nm technology nodes & designs and worked on 12FFC & 16FFC. ∴ Expertise on Synthesis, Bump Routing, Floor-planning, Power-planning, Place, CTS, Routing & Signal Integrity (Cross-talk, EM & Antenna Effect). ∴ Expertise on Lower Power Designs & has worked on all LP type blocks (On-OFF & Multi-voltage blocks). ∴ Having good understanding and hands on experience in DRC, LVS, VSI, IR & EM fixes, Antenna fixes & Sign-off metrics. ∴ Experienced on STA, timing ECOs, functional ECOs, & metal ECOs implementation. ∴ Having good understanding on DFM & DFT and hands on experience on Low Power techniques. ∴ Expertise in writing/modifying any complex scripts in TCL, Perl, Python & Unix.
Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in low-power ASIC design.
Location: Hyderabad, Telangana, India
Experience: 7 yrs 10 mos
Skills
- Physical Design
- Low-power Design
Career Highlights
- 5+ years of expertise in VLSI and ASIC Physical Design.
- Proficient in advanced technology nodes from 5nm to 90nm.
- Strong scripting skills in TCL, Perl, and Python.
Work Experience
NVIDIA
Senior Physical Design Engineer (2 yrs 3 mos)
MosChip
Senior Physical Design Engineer (5 yrs 2 mos)
Institute of Silicon Systems Pvt. Ltd.
Physical Design Trainee (5 mos)
Education
at Velagapudi RamaKrishna Siddhartha Engineering College, Vasantha Nagar, Kanuru, Vijayawada-520007(CC
Diploma at A.A.N.M & V.V.R.S.R Polytechnic College
