R

Rituraj yadav

Software Engineer

Noida, Uttar Pradesh, India6 yrs experience
Most Likely To Switch

Key Highlights

  • Expertise in Physical Design and VLSI methodologies.
  • Proficient in Synopsys and Cadence tools for design.
  • Strong background in broadband and networking technologies.
Stackforce AI infers this person is a Physical Design Engineer with expertise in VLSI and broadband technologies.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing AnalysisFloor Planning

Other Skills

Synopsys toolsClock Tree SynthesisDesign Rule Checking (DRC)ICCPNRFloor PlansRoutingPlacementctsBroadband NetworksNetworkingSatellite Communications (SATCOM)Wireless BroadbandCable BroadbandDebugging

About

Physical design engineer

Experience

6 yrs
Total Experience
1 yr
Average Tenure
2 yrs 2 mos
Current Experience

Digicomm semiconductor

Sr physical design engineer

Apr 2024 – Present · 2 yrs 2 mos · Noida · On-site

Tecquire solutions pvt ltd

Physical Design Engineer

Dec 2022 – Apr 2024 · 1 yr 4 mos · Noida, Uttar Pradesh, India · On-site

Synopsys toolsPhysical DesignClock Tree SynthesisStatic Timing AnalysisDesign Rule Checking (DRC)ICC

Insemi technology services pvt. ltd.

Physical Design Engineer

Oct 2021 – Nov 2022 · 1 yr 1 mo · Bengaluru, Karnataka, India

PNRFloor PlansRoutingPlacementctsICC+2

Vlsiguru training institute

Trainee

Sep 2018 – Aug 2019 · 11 mos · banglore, india

Broadband NetworksNetworkingSatellite Communications (SATCOM)Wireless Broadband

Hathway cable & datacom ltd

broadband technician at internship program

May 2016 – Aug 2016 · 3 mos · New Delhi Area, India

Bharat sanchar nigam limited

Telecommunications Technician at Bharat Sanchar Nigam Limited

May 2015 – Aug 2015 · 3 mos · Rewari Area, India

Education

Deenbandhu Chhotu Ram University of Science & Technology

Master of Technology - MTech — VLSI

Jun 2019 – Aug 2021

Malaviya National Institute of Technology Jaipur

workshop — VLSI

Jan 2020 – Jan 2020

Guru Jambheshwar University

Bachelor of Technology — ECE

Jan 2013 – Jan 2017

Stackforce found 100+ more professionals with Physical Design & Static Timing Analysis

Explore similar profiles based on matching skills and experience

ABHINANDAN .

ABHINANDAN .

Analog Design Engineer (External)

at Synopsys Inc

Una, India2 yrs exp
Analog Circuit Design
Sreekanth Billupati

Sreekanth Billupati

Digital Design Engineer

at C2i Semiconductors

Sri Potti Sriramulu Nellore, India6 yrs 11 mos exp
Product Design5G New Radio (NR)Team Leadership
Varun Kumar

Varun Kumar

Synthesis/STA Engineer (Contractor)

at AMD

Hyderabad, India1 yr 1 mo exp
Integrated Circuit DesignPhysical Design
Ankur Kumar

Ankur Kumar

Senior Flight Software Enginner

at Pixxel

Bengaluru, India5 yrs 6 mos exp
Embedded LinuxFPGA DesignRTL DesignVerification and ValidationSubject Matter Expertise
Basannagouda Reddy

Basannagouda Reddy

Director R&D

at Synopsys Inc

San Francisco, United States23 yrs 2 mos exp
Venkata Durga Prabhas Allacheruvu

Venkata Durga Prabhas Allacheruvu

ASIC Design Verification Engineer SpanIdea Systems @ Broadcom

at SpanIdea Systems

Guntur, India1 yr 11 mos exp
ASIC / SoC VerificationUVMVerification and Validation (V&V)
Vijayalaxmi Raddiyavar

Vijayalaxmi Raddiyavar

SRAM library validation

at Intel

Bengaluru, India4 yrs 6 mos exp
SRAMLibrary ValidationComponent DesignPDK ValidationSimulation
Jeevan Kishore Challa

Jeevan Kishore Challa

Senior Physical Design Engineer

at Qualcomm

Hyderabad, India5 yrs 7 mos exp
Physical DesignTeaching