Sachin Raj Aggarwal

Software Engineer

Delhi, India14 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in FPGA and ASIC verification methodologies.
Proficient in SystemVerilog and UVM for design verification.
Strong background in VLSI design and verification projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and FPGA design.

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Skills

Core Skills

FpgaAsic VerificationVlsi

Other Skills

Testbench environment developmentOVMUVMSystemVerilogPerlTclVMMVERILOGTANNERMATLABMODELSIMTeam ManagementCHTMLC++

About

ENGINEER VLSI - domain verification FPGA/ASIC; M.Tech. (VLSI Design) from C-DAC, Noida Engineer VLSI with 2.8 yrs. FPGA/ASIC Verification - Testbench environment development, coverage RTL Coding using OVM/UVM methodologies, SystemVerilog, Perl & Tcl In-depth knowledge of debug tools, logic design concepts & simulators i.e. VC, Questa, DVE, KIEL Developed IPs, Verification infrastructure i.e. generators, drivers, monitors, checkers etc. Recent Projects – MC Top level design Verification having sub-blocks [as Real MIPS, SPI Controller, Flash Memory and AES, CMAC blocks for data security]; QUAD SPI verification IP; Verification IP of I2C Slave; Triton (HDMI & MHL); HDMI2MHL Bridge; I2C Slave Host Bridge; Flipper (I2C Master) Also Worked on Backend projects - Single Bit Dual Port SRAM Cell Design and Frontend projects - AMBA AHB bus interface, Timer, FIFO M. Tech. (VLSI Design); GATE qualified, B. Tech. (Electronics & Comm. Eng) with high accolades Please contact me on email id - sachinrajagg87@gmail.com or phone no. 9289936717, 9250619088

Experience

14 yrs 2 mos

Total Experience

3 yrs 6 mos

Average Tenure

9 yrs 9 mos

Current Experience

Confidential

Senior Engineer

Sep 2016 – Present · 9 yrs 9 mos · Noida, Uttar Pradesh, India

Verification and designing in Semiconductor Industry

FPGAASIC VerificationTestbench environment developmentOVMUVMSystemVerilog+2

Amd r&d center india pvt ltd

Design Engineer-II

Aug 2015 – Sep 2016 · 1 yr 1 mo · Greater Hyderabad Area

Solarflare india pvt ltd

Engineer Verification

Mar 2013 – Aug 2015 · 2 yrs 5 mos · New Delhi

2.2 yrs. ASIC Verification using System Verilog, testbenches on UVM/VMM methodologies
Current projects – MC Top level design incldg. sub-blocks - Real MIPS, SPY Controller, Flash Memory and AES (Advance Encryption Standard), CMAC (Cipher based Message Authentication Code) blocks for data security (Verification using UVM & OVM methodologies & SystemVerilog); Triton (HDMI Port); Verification IP of I2C Slave in UVM & System Verilog etc.

SystemVerilogUVMVMMASIC Verification