Sagar Sorathiya — Software Engineer
Technical Skills : ASIC Digital Design using Verilog/System Verilog Strong Digital Electronics and RTL Design Skill.
Stackforce AI infers this person is a Digital Design Engineer with a focus on ASIC and RTL methodologies.
Location: Ahmedabad, Gujarat, India
Experience: 10 mos
Skills
- Asic Digital Design
- Rtl Design
Career Highlights
- Expert in ASIC Digital Design and RTL Design.
- Strong foundation in digital electronics and verification methodologies.
- Proficient in SystemVerilog and USB3.0 technologies.
Work Experience
Synopsys Inc
Graduate Engineer Trainee (10 mos)
eInfochips (An Arrow Company)
ASIC Design Intern (Summer) (1 mo)
Education
ME at Birla Institute of Technology and Science, Pilani
B.Tech in Electronics and communications engineering at Nirma University
