S

sahana y m

Software Engineer

Bengaluru, Karnataka, India1 yr 11 mos experience
Most Likely To Switch

Key Highlights

  • Experienced DFT Design Engineer at Intel.
  • Specialized in VLSI design and development.
  • Proficient in multiple programming languages and tools.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in DFT methodologies.

Contact

sahanasonu7777@gmail.comLinkedIn

Skills

Core Skills

DftVlsi

Other Skills

SQLFront-End DevelopmentASICTCLStatic Timing AnalysisAnalog Circuit DesignAnalog-to-Digital Converters (ADC)Digital Circuit DesignNI MultisimMATLABLinuxVerilogEmbedded CPython (Programming Language)C++

Experience

1 yr 11 mos
Total Experience
11 mos
Average Tenure
1 yr
Current Experience

Intel corporation

2 roles

DFT SOC DESIGN ENGINEER

Jun 2025 – Present · 1 yr

DFTVLSI

DFT design Intern

Aug 2024 – May 2025 · 9 mos

  • SOC DFT design Intern

Tata motors

Graduate Engineering Trainee

Aug 2022 – Jul 2023 · 11 mos

SQLFront-End Development

Education

Vellore Institute of Technology

Master's degree in VLSI

Aug 2023 – May 2025

Vellore Institute of Technology

Bachelor of Technology - BTech

Jan 2018 – Jan 2022

Stackforce found 100+ more professionals with Dft & Vlsi

Explore similar profiles based on matching skills and experience

Senthil Kumar Murugaiah

Senthil Kumar Murugaiah

Sr. Manager Silicon Design Engineering

at AMD

Hyderabad, India25 yrs 8 mos exp
Product ManagementEngineering Management
Sushil Sirsat

Sushil Sirsat

Research Scholar

at Visvesvaraya National Institute of Technology

India12 yrs 7 mos exp
Analog Integrated Circuit DesignSignal Integrity
Sreekanth Billupati

Sreekanth Billupati

Digital Design Engineer

at C2i Semiconductors

Sri Potti Sriramulu Nellore, India6 yrs 11 mos exp
Product Design5G New Radio (NR)Team Leadership
DP

Devesh Prajapat

Analog Circuit Design Engineer II

at Cadence

Bikaner, India3 yrs 4 mos exp
Mixed-Signal IC DesignAnalog Integrated Circuit DesignDigital Circuit Design
Varun Kumar

Varun Kumar

Synthesis/STA Engineer (Contractor)

at AMD

Hyderabad, India1 yr 1 mo exp
Integrated Circuit DesignPhysical Design
Basannagouda Reddy

Basannagouda Reddy

Director R&D

at Synopsys Inc

San Francisco, United States23 yrs 2 mos exp
BAJAMMA SHAIK

BAJAMMA SHAIK

Physical Design Engineer

at HCLTech

Guntur, India1 yr 1 mo exp
Physical DesignVLSI
Neeraj Parmar

Neeraj Parmar

Intern

at AMD

Indore, India5 mos exp
Field-Programmable Gate Arrays (FPGA)