salma jabeen

Software Engineer

Hyderabad, Telangana, India4 yrs 9 mos experience

Key Highlights

  • Proficient in Lint and verification methodologies.
  • Hands-on experience with Soc and Subsystem checks.
  • Strong foundation in Verilog and SystemVerilog.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in verification and linting processes.

Contact

LinkedIn

Skills

Core Skills

LintVerilog

Other Skills

ExiteSpyglass LintQuesta CDCSpyglass CDCQuesta RDCSpyglass RDCSystemVerilogFishtailSynopsys PrimetimeRTL CodingUniversal Verification Methodology (UVM)AXIAPBAMBADesign Tools

Experience

4 yrs 9 mos
Total Experience
1 yr 10 mos
Average Tenure
1 yr
Current Experience

Scaledge technology

Design Engineer

Jun 2025 – Present · 1 yr

Amd

Silicon Design Engineer

May 2024 – Present · 2 yrs 1 mo · Hyderabad, Telangana, India · On-site

  • Working as contractor in AMD, worked on unit testing,worked on regression, cdc, rdc, lint, clp, syn,sdcqa, tcl scripting.
  • Creating environment setup for lint,cdc,rdc,fishtail
  • Soc and Subsystem lint checks with Spyglass Lint.
  • Soc and Subsystem level CDC checks with Questa CDC and Spyglass CDC
  • Soc and Subsystem level RDC checks with Questa RDC and Spyglass RDC
  • Ownership of Excite Setup
  • Completed Assigned tasks on time .
LintExite

Sion semiconductors private limited

RTL Design Engineer

Jun 2022 – May 2025 · 2 yrs 11 mos · Hyderabad, Telangana, India · On-site

VerilogSystemVerilog

Maven silicon

Internship Trainee

Mar 2013 – Jan 2014 · 10 mos

VerilogSystemVerilog

Education

Muffakham Jah College of Engineering & Technology

Master of Technology - MTech

Gokaraju Rangaraju Institute of Engineering and Technology

B.Tech

KL University

Research Scholar

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