Samika Datta

Product Engineer

Bengaluru, Karnataka, India7 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 4 years in Post Silicon Validation at Intel.
  • Automated testing methodologies, reducing execution time significantly.
  • Recognized for contributions to PCIe and CXL validation.
Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in Post Silicon processes.

Contact

LinkedIn

Skills

Core Skills

Post Silicon ValidationTest AutomationFirmware Testing

Other Skills

PCIeCXLTest Plan CreationDebuggingAutomationStress TestingCollaborationRobustness TestingPythonNI TeststandMicrosoft PowerPointCResearchPublic SpeakingProgramming

About

An undergraduate in Electronics and Communication from NIT Rourkela, I bring over 4 years of experience in Post Silicon Validation of Intel Server CPU products. I have been an integral part of multiple Power-Ons in the HSIO technology i.e. PCIe and CXL protocols.

Experience

7 yrs 10 mos
Total Experience
3 yrs 11 mos
Average Tenure
5 yrs 9 mos
Current Experience

Intel corporation

Server SoC Post Silicon Validation Engineer

Aug 2020 – Present · 5 yrs 9 mos · India · On-site

  • Responsible for post silicon validation of PCIe and CXL Hotplug feature for Intel Xeon Data Center Products starting from test plan creation till execution and debug.
  • Found many CPLD, firmware bugs during the validation phase.
  • Partially automated the hotplug testing methodology which reduced execution time significantly and helped in stress testing for which I received recognition from the India Post-Si team.
  • Responsible for validating many PCIe RAS scenarios as well .
  • Involved in bring up of an Intel PCIe Gen5 testcard , collaborated with Testcard Design and Firmware teams for stabilizing the Gen5 link.
  • Currently ramping up on OOBMSM ( Out of Band Management and Services Module) IP.
Post Silicon ValidationPCIeCXLTest Plan CreationDebuggingAutomation+2

Schneider electric

2 roles

Product Verification Engineer

Apr 2019 – Aug 2020 · 1 yr 4 mos

  • Firmware testing of Low Voltage Circuit breakers and gateways including robustness testing in stressed conditions
  • Creation of new test cases for new features
  • Automation of test cases using NI Teststand tool and Python scripts
Firmware TestingRobustness TestingTest AutomationPythonNI Teststand

Graduate Engineer Trainee

Jul 2018 – Apr 2019 · 9 mos

Iit hyderabad

Summer Intern

May 2017 – Jul 2017 · 2 mos · Hyderabad, Telangana

  • Studied about the different types of regression methods used to solve an Ordinary Least Squares problem to determine which method is the best.

Education

National Institute of Technology Rourkela

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2014 – Jan 2018

Ravenshaw Junior College

Intermediate — Science

Jan 2012 – Jan 2014

Cambridge School

Matriculation(ICSE)

Jan 2000 – Jan 2012

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