Sang pri Singh

DevOps Engineer

Greater Delhi, Delhi, India2 yrs experience

Highly Stable

Key Highlights

Led PCIe IP verification with 100% assertion coverage.
Reduced report generation time from 4 hours to 2 minutes.
Improved regression efficiency through automation scripting.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in UVM and PCIe IP.

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Skills

Core Skills

UvmPcie IpSystemverilog

Other Skills

Static Timing AnalysisPython (Programming Language)Assertions (SVA)Universal Verification Methodology (UVM)AXIAPBRISC-VLinuxScriptingCDCVerilogDigital ElectronicsC++C (Programming Language)system verilog

About

Verification Engineer with ~2 years of experience in DV, specialization in PCIe IP. Strong working knowledge of industry-standard EDA tools including Synopsys VCS, Verdi, and EMAN for simulation, debugging, waveform analysis, and regression management. Strong expertise in UVM,SystemVerilog/Verilog, assertions(SVA), debugging, coverage. Experienced in writing reusable verification components and building automation scripts using Python to improve regression efficiency and debug productivity.

Experience

2 yrs

Total Experience

2 yrs

Average Tenure

2 yrs

Current Experience

Synopsys inc

IP Verification Engineer (PCIe)

Jun 2024 – Present · 2 yrs · Noida · On-site

Led pre-silicon verification of PCIe4 PHY IP, validating its functionality in UVM-based reusable verification environments, (PCIe IP , UVM)
Enhanced assertion-based verification (SVA) by refining and adding assertions, directly from the protocol spec. , achieving 100% assertion coverage
Executed and analyzed multi-configuration regressions, performed root-cause analysis, raise jira for issue and collaborated with RTL teams to resolve design and testbench issues
Defined verification strategy and contributed to test plan development, ensuring comprehensive coverage of PCIe IP features and corner cases
Debugged compilation and simulation failures, performing R2R and POP testing to ensure regression stability and cross- version tool reliability.Collaborated with RTL teams to understand microarchitecture and debug functional issues.
Reduced incoming customer JIRAs by 10 percent through proactive issue identification, early-stage validation and workflow improvements.
Developed Python scripts to parse regression logs, extract failures, identify trends, and generate consolidated
regression summaries using AI. Reduced manual triage effort and improved OST operational efficiency, time taken for reports from 4 hours to less than 2mins.

Static Timing AnalysisPython (Programming Language)UVMPCIe IPAssertions (SVA)