S

Sanjay Kumar Surshetty

Software Engineer

Bengaluru, Karnataka, India5 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in VLSI design with hands-on experience in multiple tech nodes.
  • Proficient in physical design tools and methodologies.
  • Strong foundation in Verilog and TCL scripting.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Implementation.

Contact

Skills

Core Skills

Pg ImplementationPhysical Design (pnr)

Other Skills

Shell ScriptingTCL scriptingVLSI DesignMATLABMicrosoft OfficeXilinx VivadoVerilog in Xilinx ISECadence Virtuosoc(basics)Code Composer StudioMicrowind

About

VLSI enthusiast...Have experience in PnR(Placement and Routing)team Bangalore.Worked in different tech nodes(N3,N5,N6,N12). I have an experience of working with ICC II Compiler,Fusion Compiler,IC validator,Redhawk and have knowledge of TCL & Shell scripting.Main focus of work is towards attaining good PPA(Power Performance Area).Have experience on PG implementation for different objectives.During academics,I have done projects related to instrumentation amplifier(area efficient and high gain) and 4-bit TIQ comparator flash ADC in CADENCE ADE which enhanced my knowledge to a great extent and also I learned much about cascading of amplifiers and how it can work as a better current source . I also know Verilog programming in XILINX ISE and have knowledge of microprocessors and assembly language programming in 8085 kit. I have an exposure towards the software like CADENCE VIRTUOSO, MATLAB...

Experience

5 yrs 8 mos
Total Experience
5 yrs
Average Tenure
8 mos
Current Experience

Marvell technology

Physical Design, Staff Engineer

Oct 2025Present · 8 mos · Hyderabad · On-site

Synopsys inc

5 roles

ASIC Physical Design, Staff engineer

Feb 2025Oct 2025 · 8 mos · Hybrid

ASIC Physical Design, Sr Engineer

Apr 2024Feb 2025 · 10 mos · Hybrid

ASIC Physical Design, Sr Engineer

Promoted

Feb 2023Jan 2024 · 11 mos

PG Implementation

ASIC Physical Design Engineer

Jul 2020Feb 2023 · 2 yrs 7 mos

  • Area of work - Physical design (Placement and Routing)
Shell ScriptingTCL scriptingPhysical Design (PnR)

Technical Intern

Jan 2020Jul 2020 · 6 mos

Bharat heavy electricals limited

Summer Training

May 2018May 2018 · 0 mo · Hyderabad, Telangana, India

  • Study of PLC basics

Education

Birla Institute of Technology, Mesra

Bachelor of Engineering — Electronics and Communications Engineering

Jan 2016Jan 2020

Texas A&M University

Master of Science - MS — Computer Engineering

Jan 2024Apr 2024

• Narayana Junior College

Intermediate

Jan 2014Jan 2016

T.V.R. Model High School

S.S.C

Jan 2014Present

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