Santosh Yadav

Director of Engineering

Bengaluru, Karnataka, India26 yrs 7 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

Proven record of successful silicon tape outs.
Expert in Physical Design for advanced technology nodes.
Strong leadership in cross-functional team collaboration.

Stackforce AI infers this person is a leader in semiconductor design and engineering, specializing in Physical Design and project management.

Contact

Skills

Core Skills

Engineering LeadershipPhysical DesignSocDesign Engineering

Other Skills

IP designingmethodologyproject executionresource planningcross functional team collaborationmethodology developmentRTL developmentschedule trackingcollateral co-developmentArtificial Intelligence trainingSOC executionphysical implementationAPR designlow power design issuesimplementation flow

About

Leading team at Intel India site, responsible for, IP designing, enabling methodology and flow, for advance technologies Driving project execution , resource planning and resolving dependencies and priority conflict to deliver design closure on schedule Enabling cross functional team to co develop and co optimize design, technology , flow and EDA capabilities by engaging them in consistent and timely manner for future technology nodes Multiple tape outs with silicon success in various technology nodes Proven record for planning and execution of Physical Design for processors, IPs and SOCs Good blend of technical expertise and managing PD projects using APR flow Hands on experience in Physical Design flow from Netlist to GDS2 using standard industry tools, Cadence and Synopsys flows Artificial Intelligence enthusiast and trainer for advance AI classes Influencer and motivator to train people get best Results at work #DesignTechnolgyPlatform

Experience

26 yrs 7 mos

Total Experience

5 yrs 3 mos

Average Tenure

10 yrs 9 mos

Current Experience

Intel corporation

2 roles

Director Of Engineering

Promoted

Jan 2022 – Present · 4 yrs 5 mos

IP designingmethodologyproject executionresource planningcross functional team collaborationEngineering Leadership+1

Engineering Manager

Aug 2015 – Dec 2021 · 6 yrs 4 mos

Leading a team responsible for developing methodology for advance process node, validating it through test chips and IP execution, including RTL development. Keeping track of schedule and dependencies from all stakeholders, co-developing collateral's and TFM dynamically. Resolving priority, dependencies and resource conflicts to ensure high silicon correlation with implementation.
Enabling engineers across Intel India to use Artificial Intelligence in their work through delivering Advance training for AI. Mentoring through management training for employees to improve efficiency in their work and better career planning for engineers at Intel India.

methodology developmentRTL developmentschedule trackingcollateral co-developmentArtificial Intelligence trainingEngineering Leadership+1

Amd

2 roles

MTS Design Engineer

Promoted

Oct 2008 – Aug 2015 · 6 yrs 10 mos

Co-ordinated SOC execution with cross functional team across different geos
Planning, prioritizing, tracking, resolving conflict in dependencies and priorities for timely closure of SOC design
Led physical implementation of multiple SOC and Core IP in node ranging from 45nm to 16 nm
Worked hands on implementation of APR design from netlist to GDS2, using industry standard tools like ICC, Prime time , Star RC , Caliber, Conformal and Redhawk
Expertise in implementation and design closure of Synchronous bussing for high frequencies
Good Knowledge of low power design issues in physical domain

SOC executionphysical implementationAPR designlow power design issuesPhysical DesignSoC

Senior Design Enginner

Oct 2008 – Jan 2012 · 3 yrs 3 mos

Physical deisgn and analysis of SOCs

Lsi technologies india pvt. ltd

Tech Lead

Jan 2007 – Jan 2008 · 1 yr

Worked on complete implementation flow from netlist to GDS2
Owned developing physical sign off flow
Developed expertise on clock Tree synthesis and optimization for power and performance
Developed expertise in APR execution of SOC for mobile communications

implementation flowclock tree synthesisAPR executionPhysical Design