Sarathy G

Software Engineer

Bengaluru, Karnataka, India5 yrs 5 mos experience

Highly Stable

Key Highlights

Senior DFT Engineer with extensive experience in ATPG.
Proficient in JTAG and scan insertion methodologies.
Strong background in VLSI design and testing.

Stackforce AI infers this person is a VLSI Design and Testing Specialist.

Contact

Skills

Core Skills

Automatic Test Pattern Generation (atpg)Joint Test Action Group (jtag)

Other Skills

AtpgScan InsertionGLS

Experience

5 yrs 5 mos

Total Experience

3 yrs

Average Tenure

2 yrs 5 mos

Current Experience

Mirafra technologies

Senior DFT Engineer

Jan 2024 – Present · 2 yrs 5 mos · Bengaluru · On-site

Working for Qualcomm

AtpgJoint Test Action Group (JTAG)Scan InsertionGLSAutomatic Test Pattern Generation (ATPG)

Ziotron consulting

DFT Engineer

Nov 2020 – Nov 2023 · 3 yrs · Bengaluru, Karnataka, India · On-site

Joint Test Action Group (JTAG)Automatic Test Pattern Generation (ATPG)

Education

SRM IST Chennai

Master of Technology - MTech — Vlsi

Jun 2015 – Jun 2017

Vel Tech Multi Tech Dr. Rangarajan Dr. Sakunthala Engineering College

Bachelor of Engineering - BE

Jun 2011 – Jun 2014

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