SHAIK NAZEER

Software Engineer

Hyderabad, Telangana, India7 yrs 7 mos experience
Highly Stable

Key Highlights

  • 7 years of experience in VLSI design and Static Timing Analysis.
  • Expertise in timing closure and constraint development.
  • Strong cross-functional collaboration skills in semiconductor solutions.
Stackforce AI infers this person is a VLSI design engineer specializing in semiconductor technology.

Contact

Skills

Core Skills

Static Timing AnalysisPhysical DesignApplication-specific Integrated Circuits (asic)Very-large-scale Integration (vlsi)

Other Skills

Timing ClosureConstraint DevelopmentSignoff AnalysisCross-Functional CollaborationProblem SolvingTCLPlace & RouteScriptingMaintenance and RepairFix & FlipConstruction Clean-upTime ClocksDelivery Of ProjectsPowerPlansConstructive Feedback

About

Experienced Physical Design Engineer with a demonstrated history of working with synopsys and services industry. Skilled in static timing analysis, know tools like prime_time, icc2_shell, dc_shell, and physical verification(drc & lvs)

Experience

7 yrs 7 mos
Total Experience
2 yrs 5 mos
Average Tenure
3 mos
Current Experience

Amd

sr.silicon design engineer

Feb 2026Present · 3 mos · Hyderabad · On-site

  • Excited to join Advanced Micro Devices (AMD) as a Senior STA Engineer!
  • With 7 years of experience in VLSI design and Static Timing Analysis, I have worked extensively on timing closure, constraint development, signoff analysis, and cross-functional collaboration across synthesis, PnR, and physical design teams.
  • Looking forward to contributing to high-performance, power-efficient semiconductor solutions and being part of cutting-edge innovation.
  • #AMD #VLSI #STA #Semiconductor #TimingClosure
Static Timing AnalysisTiming ClosureConstraint DevelopmentSignoff AnalysisCross-Functional CollaborationPhysical Design

Synopsys inc

2 roles

ASIC Physical Design, Staff Engineer

Feb 2025Feb 2026 · 1 yr · Hyderabad, Telangana, India

ASIC Physical Design Engineer II

Aug 2021Feb 2025 · 3 yrs 6 mos · Hyderabad, Telangana, India

Problem SolvingApplication-Specific Integrated Circuits (ASIC)

Insemi technology services pvt. ltd.

Physical Design Engineer

Apr 2020Aug 2021 · 1 yr 4 mos · Bengaluru, Karnataka

TCLPlace & Route

Ambit semiconductors

Physical Design Engineer

Oct 2018Apr 2020 · 1 yr 6 mos · Bangalore

TCLPlace & Route

Dkop labs pvt. ltd.

Assistant Trainer

May 2018Jun 2018 · 1 mo · Noida Area, India

  • assisted students on Verilog, Linux, System Verilog.
Very-Large-Scale Integration (VLSI)Scripting

Education

lovely professional universiy

Bachelor of Technology (BTech) hons

Jan 2014Jan 2018

Dkop labs

training — vlsi design and verification

Jan 2018Jan 2018

sri chaitanya junior college

High School Diploma

Jan 2012Jan 2014

Lovely Professional University

Bachelor of Technology

Jan 2014Jan 2018

Pragathi

High School Diploma

Jan 2010Jan 2012

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