Manish Saxena

Software Engineer

Bengaluru, Karnataka, India18 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC and VLSI design methodologies.
  • Proven leadership in semiconductor engineering.
  • Extensive experience in RTL design and verification.
Stackforce AI infers this person is a semiconductor design expert with extensive experience in ASIC and VLSI technologies.

Contact

LinkedIn

Skills

Core Skills

AsicVlsi

Other Skills

VerilogSoCSystemVerilogRTL designEDAStatic Timing AnalysisCadence VirtuosoIntegrated Circuit DesignPhysical DesignNCSimModelSimFunctional VerificationDebuggingApplication-Specific Integrated Circuits (ASIC)

Experience

18 yrs 10 mos
Total Experience
6 yrs 3 mos
Average Tenure
9 yrs 5 mos
Current Experience

Qualcomm

3 roles

Senior Staff Engineer/Manager

Promoted

Aug 2020 – Present · 5 yrs 9 mos

VLSIVerilogASICSoCSystemVerilogRTL design+10

Senior Staff Engineer

Dec 2019 – Jul 2020 · 7 mos

Staff Engineer

Oct 2016 – Nov 2019 · 3 yrs 1 mo

Marvell semiconductor

3 roles

Staff Engineer, ASIC Design

Apr 2014 – Oct 2016 · 2 yrs 6 mos · Bengaluru, Karnataka, India

Senior Engineer, ASIC Design

Promoted

Sep 2012 – Mar 2014 · 1 yr 6 mos · Bengaluru, Karnataka, India

ASIC Design Engineer

Jan 2011 – Aug 2012 · 1 yr 7 mos · Bengaluru, Karnataka, India

Samsung electronics

Design Engineer

Feb 2007 – Dec 2010 · 3 yrs 10 mos

  • Worked in Semiconductor Solutions Team

Education

BITS, Pilani

ME — Microelectronics

Jan 2004 – Jan 2006

Government Engineering College, Ujjain

BE — Electronics & Telecommunication

Jan 1999 – Jan 2003

St. Clares Senior Secondary School, Agra Cantt

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