Shanie George

CEO

San Francisco, California, United States24 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 22 years in semiconductor R&D leadership.
Expert in optimizing Power, Performance, and Area targets.
Proven track record in achieving first-pass silicon success.

Stackforce AI infers this person is a Semiconductor R&D leader with expertise in advanced SoC design and library architecture.

Contact

Skills

Core Skills

Library ArchitectureProject ManagementStandard Cell Design

Other Skills

Synopsys Custom CompilerLibrary ArchitectLibrary Architecture Exploration and DefinitionStandard Cell Circuit DesignHierarchical Layout designSimulationCircuit DesignSimulationsASICVLSICadence VirtuosoVerilogSPICETCLLVS

About

As a seasoned Senior Director with over 22 years of experience in semiconductor R&D, I lead high-impact, global engineering teams in the design, development, and delivery of state-of-the-art standard cell libraries of latest technology nodes across multiple foundries for advanced SoCs. My expertise spans the entire product life cycle, from Library Architecture definition, Methodology development and Design-Technology Co-Optimization (DTCO) with foundry partners to achieving first-pass silicon success across multiple generations of technology nodes. I have a proven track record of driving strategic initiatives to optimize Power, Performance, and Area (PPA) targets while ensuring robust reliability. My leadership philosophy centers on technical excellence, cross-functional collaboration, and mentoring top-tier talent, enabling efficient execution and seamless integration with physical design, CAD, and product teams. I am passionate about pushing the boundaries of microelectronics and translating complex technical challenges into successful business solutions.

Experience

24 yrs 11 mos

Total Experience

6 yrs 2 mos

Average Tenure

11 yrs 10 mos

Current Experience

Synopsys inc

5 roles

Sr Director R & D

Promoted

Feb 2024 – Present · 2 yrs 4 mos

Synopsys Custom CompilerProject ManagementLibrary ArchitectLibrary Architecture Exploration and DefinitionStandard Cell Circuit DesignHierarchical Layout design+16

R&D Director

Promoted

Feb 2023 – Feb 2024 · 1 yr

Sr. Manager R & D

Jan 2019 – Jan 2023 · 4 yrs

Sr. Staff R & D Engineer

Jun 2018 – Jan 2019 · 7 mos

Staff R & D Engineer

Jul 2014 – Jun 2018 · 3 yrs 11 mos

Lsi corporation

2 roles

Staff Circuit Design Engineer

Apr 2007 – May 2014 · 7 yrs 1 mo

Member of the Standard Cell design team of LSI’s Foundry Technology & Circuits Group.
Recently this team delivered LSI’s performance, density and compact router friendly Standard Cell libraries for TSMCs 16FF technology. Worked on sizing of standard cells, simulation, hierarchical layout development with Cadence Virtuoso, DRC/LVS verification , DFM analysis and pin analysis. Generated layouts for the preliminary library for TSMC 16FF+ process. Have experience in circuit design ,simulation and layout generation in TSMC 20nm,28 nm ,45nm & 65nm technology nodes. Have experience in configuring automated layout generation tool in 28nm,45nm & 65nm technology nodes.

Cadence VirtuosoStandard Cell Design

Sr. Modeling Design Engineer

Feb 2005 – Apr 2007 · 2 yrs 2 mos

Was Member of Essential IP Deliverable Generation team of LSI Logic which supports the Modeling of libraries for Worldwide LSI Logic.Was responsible for third party Physical Modeling for the entire range of LSI Libraries (65nm, 90nm, 130 nm) used by all LSI internal & external Customers.