Shashidhar Kondaguli

Product Engineer

Bengaluru, Karnataka, India8 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expertise in VLSI and ASIC design methodologies.
  • Hands-on experience with Static Timing Analysis and Physical Design.
  • Proven track record at leading tech companies like Intel.
Stackforce AI infers this person is a VLSI and ASIC design engineer with strong expertise in physical design and verification.

Contact

LinkedIn

Skills

Core Skills

Very-large-scale Integration (vlsi)

Other Skills

Design Rule Checking (DRC)RTL DesignStatic Timing AnalysisApplication-Specific Integrated Circuits (ASIC)FloorplanningPlacementSTAPerlPhysical DesignConjestion removalHandled conjested partitionsTCLECOLayout Versus Schematic (LVS)Place & Route

About

I have good knowledge ASIC flow, Floor planning, Placement, STA, CTS, Routing. Basic knowledge of PERL,Tcl. Basic knowledge of RTL design and verification. Worked in Prime Time for time fixes and have hands on. I have completed one year in Intel. And one year in Altran.

Experience

8 yrs
Total Experience
2 yrs
Average Tenure
5 yrs 1 mo
Current Experience

Wipro

ASIC Physical Design Engineer

May 2021 – Present · 5 yrs 1 mo · Bengaluru, Karnataka, India · Hybrid

Very-Large-Scale Integration (VLSI)Design Rule Checking (DRC)

Altran

Design Engineer 2

May 2018 – Aug 2019 · 1 yr 3 mos · Bengaluru, Karnataka, India

Very-Large-Scale Integration (VLSI)RTL Design

Intel corporation

Graphics Hardware Engineer

Mar 2017 – Apr 2018 · 1 yr 1 mo · Bangalore

Very-Large-Scale Integration (VLSI)RTL Design

Rv-vlsi vlsi and embedded systems design center

Physical Design Engineer

Aug 2016 – Mar 2017 · 7 mos · Bangalore

Education

RV VLSI

PHYSICAL DESIGN BACK END — physical design

Jan 2016 – Jan 2017

VDRIT HALIYAL

Bachelor's degree

Jan 2012 – Jan 2016

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