Shishpal Kushwah

VP of Engineering

Bengaluru, Karnataka, India14 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and Static Timing Analysis.
  • Proven track record in low power physical design projects.
  • Extensive experience with ASIC and VLSI technologies.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and ASIC development.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

ASICPrimetimeDRCTCLVLSIClock Tree SynthesisFirst EncounterVerilogVHDLTiming ClosureFloorplanningPerlICCPhysical VerificationPlace & Route

Experience

14 yrs 1 mo
Total Experience
3 yrs 6 mos
Average Tenure
8 yrs 8 mos
Current Experience

Qualcomm

3 roles

Engineer Senior Staff/Manager

Promoted

Dec 2023 – Present · 2 yrs 6 mos

Physical DesignStatic Timing AnalysisASICPrimetimeDRCTCL+23

Staff Engineer

Dec 2020 – Dec 2023 · 3 yrs

Lead Engineer

Oct 2017 – Dec 2020 · 3 yrs 2 mos

Amd

Physical Design Engineer

Aug 2015 – Oct 2017 · 2 yrs 2 mos · Greater Hyderabad Area

Mediatek inc.

Physical Design Engineer

Nov 2014 – Jul 2015 · 8 mos · Bengaluru, Karnataka, India

  • I was working at MediaTek Inc. as a Physical Design Engineer through Synapse Design Automation Inc.

Amd

Physical Design Engineer

Jan 2012 – Aug 2014 · 2 yrs 7 mos · Greater Hyderabad Area

  • Worked at AMD Hyderabad as a Physical Design Engineer through Einfochips India Pvt.Ltd.
  • Worked on three low power physical design project on 28nm technology.
  • Involved in P&R , Timing & MVRC closure, Physical verification checks at block level.
  • Worked on multi voltage timing for multi voltage islands.

Einfochips

Physical Design Engineer

Oct 2011 – Dec 2011 · 2 mos · Greater Ahmedabad Area

Eitra - einfochips training & research academy ltd

Traniee

Jul 2011 – Sep 2011 · 2 mos · Greater Ahmedabad Area

Education

Charotar Institute of Technology

Gujarat University

Jan 2007 – Jan 2011

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