Sep 2022 – Feb 2026 · 3 yrs 5 mos

• AI Computing

Jul 2022 – Sep 2022 · 2 mos

Jun 2019 – Jun 2022 · 3 yrs

• Palladium and Protium R&D

Feb 2016 – Jun 2019 · 3 yrs 4 mos

• Design Compiler
• SYNOPSYS R&D ---- C/C++ (Unix Environment) + Scripting
• Roles
• 1. Logic Synthesis -Design Compiler (R&D) - Worked on the flagship product of Synopsys, Design Compiler, which is the best VLSI synthesis tool in the EDA market.
• I. Working on all major optimization engines and improving the PPA (QoR) of the product.
• II. I have worked on multiple projects to improve Area, Timing and Leakage of designs.
• III. I have implemented multiple significant runtime and performance improvement projects.
• IV. II. Handling customer-raised critical issues.
• 2. Code quality
• I. Static Analysis (Coverity).
• II. Dynamic Analysis (IBM Purify)
• 3. Formal verification - Formality Triaging for DC
• I. verifying that the logic design conforms to specification.

Jun 2014 – Feb 2016 · 1 yr 8 mos

• SYNOPSYS R&D ---- C/C++ (Unix Environment)
• Roles
• 1. Logic Synthesis -Design Compiler (R&D) -
• I. Logic synthesis is a process by which an abstract form of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates
• II. Worked for the Logic Synthesis tool development in Logic Optimization R&D team
• 2. Code quality
• I. Static Analysis (Coverity).
• II. Dynamic Analysis (IBM Purify)
• 3.Formal verification - Formality Triaging for DC
• I. verifying that the logic design conforms to specification.

Jun 2009 – Jul 2009 · 1 mo · noida

• Web Application development