Shreya Gupta

Software Engineer

Bangalore, Karnataka, India0 mo experience

Key Highlights

Awarded best paper at DAC 2020 for innovative algorithm.
Designed power estimation workflow improving accuracy.
Automated workflows, enhancing team efficiency.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and power optimization.

Contact

shreya121098@gmail.com LinkedIn

Skills

Core Skills

Vlsi DesignPower OptimizationPower AnalysisWorkflow Automation

Other Skills

AbacusApplication-Specific Integrated Circuits (ASIC)BashBootstrapCCSHCadence JoulesCascading Style Sheets (CSS)DebuggingDigital ElectronicsEnglishGenusHTMLHTML5Innovue

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Texas instruments

2 roles

Digital Design Engineer

Aug 2020 – Present · 5 yrs 10 mos

Digital Design Intern

May 2019 – Nov 2019 · 6 mos · Bengaluru, Karnataka, India · On-site

Developed a Weighted Partial Gating Selection Algorithm to optimize power reduction in scan-based tests, selecting logic gates for gating in the test mode efficiently. This paper recieved the best paper award at DAC 2020.
Designed and implemented an early power estimation workflow using Cadence Joules, improving power analysis accuracy by benchmarking results against Voltus.
Automated multiple Physical Design team workflows by scripting in TCL, CSH, and PERL, reducing manual effort and improving efficiency.
Analyzed test power consumption trends and provided optimization strategies for reducing dynamic power in digital designs.
Gained hands-on experience in VLSI design methodologies, focusing on Physical Design, Static Timing Analysis (STA), and Power Analysis.

Weighted Partial Gating Selection AlgorithmCadence JoulesVoltusTCLCSHPERL+5