Shubham Gupta

Software Engineer

New Delhi, Delhi, India3 yrs 9 mos experience

Most Likely To Switch

Key Highlights

Expert in RTL coding and debugging for SOCs/IPs.
Proficient in static verification checks including LINT and STA.
Experience in large scale 5G telecommunications projects.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in telecommunications and FPGA development.

Contact

Skills

Core Skills

Rtl DesignLogic Design

Other Skills

Verilog HDLLINT ChecksCDCRDCSTAStatic Timing AnalysisAXI4-Stream Data ProtocolLogic OptimizationXilinx Design Constraint (XDC)RTL DevelopmentVery-Large-Scale Integration (VLSI)Field-Programmable Gate Arrays (FPGA)Application-Specific Integrated Circuits (ASIC)Digital ElectronicsRTL Coding

About

My profile involves me in RTL coding and debugging SOCs/IPs for static verification checks which includes the proficient knowledge of LINT checks, CDC (Clock Domain Crossing), and STA (Static Timing Analysis). Electronics Engineer looking for opportunities in VLSI/semiconductor industry having exposure to Xilinx ISE, Xilinx Vivado, ModelSim/QuestaSim tool and gVim text editor.

Experience

3 yrs 9 mos

Total Experience

1 yr 10 mos

Average Tenure

2 yrs 2 mos

Current Experience

Intel corporation

RTL Design Engineer

Mar 2024 – Present · 2 yrs 2 mos · Bengaluru, Karnataka, India

Logic DesignVerilog HDLRTL Design

Indian institute of technology, madras

Project Associate (FPGA Design Engineer)

Aug 2022 – Mar 2024 · 1 yr 7 mos · Chennai, Tamil Nadu, India

My profile involves me in RTL coding and debugging SOCs/IPs for static verification checks which includes the proficient knowledge of LINT checks, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing) checks and STA (Static Timing Analysis).
Working on large scale 5G testbed project funded by Department of Telecommunication (DoT), Govt. of India as a FPGA Design Engineer job profile.

Logic DesignVerilog HDLLINT ChecksCDCRDCSTA+1