Ganapathi S. — CTO

Technical Skills Hardware Description Language : Verilog, VHDL Hardware Verification Language : e-language,VERA Software Language : C, C++ Tools : ModelSim, Finsim, Specman, Design Complier, Ambit, PrimeTime, LEC, Synplify Pro, Xilinx XST, DC Lint, Spyglass Editors : Vim, Emacs Software Tools : CVS, Gnat Bug tracking Tool Scripting Languages : TCL, Perl, Shell Script, Make Protocols : TCP/IP, WLAN MAC IEEE 802.11, SDR, DDR, DDR2, SDRAM,USB Operating Systems : Linux, Windows Experience Summary • 15+ years of extensive experience in ASIC / FPGA design and verification • Expert in Micro architecture, logic design and Implementation • Excellent Debugging and analysis skills • Designed the architecture of WLAN 802.11 MAC transmit path • Designed the architecture SDRAM controller compatible to both DDR/SDR SDRAM, Cache controller and Cache Search Engine • Designed the architecture of Packet Classify Engine, TCP Engine Verification Environment • Designed the architecture of ACL-Qos-Tunnel Engine, Eqos, Ingress Vlan Mapping Process, Queue Adapter Submodule’s • Designed the architecture of Request Table, Grant Table, Fabric Output

Stackforce AI infers this person is a seasoned ASIC/FPGA design expert in the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 25 yrs 5 mos