Shubham Kumar

DevOps Engineer

Bengaluru, Karnataka, India7 yrs 11 mos experience

Key Highlights

  • Expert in memory compiler design for advanced nodes.
  • Strong background in EMIR and IR analysis.
  • Proficient in multiple scripting languages for automation.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in memory compilers and power integrity analysis.

Contact

Skills

Core Skills

EmirGrid RobustnessMemory Layout DesignSram

Other Skills

static and dynamic IR AnalysisCAM memoriesTCAMmemory compilersPerlTcl-TklayoutBashLayout Versus Schematic (LVS)Design Rule Checking (DRC)CMOSMixed SignalVirtuosoAnalog CircuitsCadence Virtuoso

About

Tools expertise : RedHawk_SC, Voltus Knowledge of PDNs. Good understanding of Grid realiablity, chip power, static and dynamic IR drop analysis Knowledge of EM of power and signal. Good knowledge of python. ------------------------------------------------------------------------------ Layout design of LUT and interconnect atoms in FPGA. Test chip on tsmc 3nm. I am currently working on different type of memory compilers, which include SRAM , Register file on state of the art tech node. I have also worked on CAM memories as well, TCAM to b specific, on TSMC 5nm node(custom memory) . Worked on : TSMC - 5nm and 7nm tech . Workedon High density sram memory compiler Samsung - 5,11nm tech. Have good knowledge of scripting language Bash ,TCL & Perl Tools used : cadence Virtuoso L, XL & EXL Physical verification: mentor calibre and Cadence assura

Experience

7 yrs 11 mos
Total Experience
2 yrs 3 mos
Average Tenure
1 yr 2 mos
Current Experience

Qualcomm

Senior Lead Engineer

Apr 2025Present · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

  • I will be working as a CAD and methodology engineer. Key area of focus - Grid Robustness, EMIR , static and dynamic IR Analysis
Grid RobustnessEMIRstatic and dynamic IR Analysis

Ansys

Application Engineer

Jan 2023Mar 2025 · 2 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Amd

IC layout engineer 2

Oct 2021Jan 2023 · 1 yr 3 mos · Hyderabad, Telangana, India

Sankalp semiconductor

Memory Layout Design Engineer

Jun 2018Oct 2021 · 3 yrs 4 mos

Memory Layout DesignSRAMCAM memoriesTCAM

Education

ABES Engineering College

B.Tech. - Bachelor of Technology

Aug 2014Jun 2018

pine training academy

VLSI

Jan 2017Jan 2018

GIC allahabad

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