Shubham Kumar — DevOps Engineer
Tools expertise : RedHawk_SC, Voltus Knowledge of PDNs. Good understanding of Grid realiablity, chip power, static and dynamic IR drop analysis Knowledge of EM of power and signal. Good knowledge of python. ------------------------------------------------------------------------------ Layout design of LUT and interconnect atoms in FPGA. Test chip on tsmc 3nm. I am currently working on different type of memory compilers, which include SRAM , Register file on state of the art tech node. I have also worked on CAM memories as well, TCAM to b specific, on TSMC 5nm node(custom memory) . Worked on : TSMC - 5nm and 7nm tech . Workedon High density sram memory compiler Samsung - 5,11nm tech. Have good knowledge of scripting language Bash ,TCL & Perl Tools used : cadence Virtuoso L, XL & EXL Physical verification: mentor calibre and Cadence assura
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in memory compilers and power integrity analysis.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 11 mos
Skills
- Emir
- Grid Robustness
- Memory Layout Design
- Sram
Career Highlights
- Expert in memory compiler design for advanced nodes.
- Strong background in EMIR and IR analysis.
- Proficient in multiple scripting languages for automation.
Work Experience
Qualcomm
Senior Lead Engineer (1 yr 2 mos)
Ansys
Application Engineer (2 yrs 2 mos)
AMD
IC layout engineer 2 (1 yr 3 mos)
Sankalp Semiconductor
Memory Layout Design Engineer (3 yrs 4 mos)
Education
B.Tech. - Bachelor of Technology at ABES Engineering College
VLSI at pine training academy
at GIC allahabad