Apr 2011 – May 2016 · 5 yrs 1 mo · Bangalore

• Custom Circuit Design and dynamic timing for the datapath in NAND Flash IP.

Nov 2009 – Mar 2011 · 1 yr 4 mos

• Currently working in the Read Channel IP verification team. Responsibilities are development of Testbench components like Monitors, Test Cases, Coverage Files and writing Assertions and Verification plans for Functional (RTL) verification of the Analog Frontend block and the Control Block of the Read Channel IP. Other responsibilities include interacting with architecture and design team based in USA and China respectively for the understanding of the Design Specifications and debugging any issues found in the design. The Monitors, Test cases, Assertions and the Coverage files are done in System Verilog. We follow the OVM methodology in our testbench.

Jan 2007 – Jul 2007 · 6 mos

• Worked on RTL Design and Verification of SD card and its interfaces. The design was done using Verilog HDL using Cadence NC Verilog tool. The Design was verified for functionality using assertions based verification and functional verification. The Design and the debugging of the SD card were done in a Linux environment.