Shuvam Podder

Software Engineer

Kolkata, West Bengal, India6 yrs 5 mos experience

Key Highlights

Expert in Mixed-Signal IC Design and Verification.
Strong foundation in VLSI and Analog Circuit Design.
Proven leadership in automotive power management projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and Mixed-Signal IC Design.

Contact

Skills

Core Skills

Mixed-signal Ic DesignAnalog Circuit DesignAmsDesign Verification TestingSilicon

Other Skills

Analog CircuitsCadence VirtuosoCircuit DesignDesignSystem on a Chip (SoC)Verilog-AMSVery-Large-Scale Integration (VLSI)FEVLDOLinuxCadenceData StructuresProgrammingAutomationVerilog

About

An ECE undergraduate with leadership qualities who is involved in the design, construction, and operation of electronic systems and devices; works in different segments of the VLSI industry, Design and Automation Industry, has specialization in electrical circuits and also VLSI Design Engineering under Make In India Program; has frequently worked with computing systems, industrial equipment, various EDA tools and Programming languages like Python, Java,, C++, C; has a solid foundation in research, design, and development of Integrated Circuits and can also work with Analytics

Experience

6 yrs 5 mos

Total Experience

1 yr 3 mos

Average Tenure

11 mos

Current Experience

Arrow electronics

Senior Analog Design Engineer

Jul 2025 – Present · 11 mos · Pune, Maharashtra, India · On-site

Automotive Power Management / FuSa / HV AMS Verification & Tapeout
Drove end-to-end AMS verification and tapeout for an automotive-grade power management IC, delivering GDSII sign-off on GF 130BCD technology.
Owned Multiple Blocks verification, completing PVT, corner, and reliability validation across power and analog sub-blocks.
Designed and verified high-voltage IO blocks (24V–40V operation, 65V ESD), aligned with automotive BCD and HV reliability requirements.
Led top-level mixed-signal integration of analog, digital, and IO ring, ensuring robust power-domain and protection strategy.
Verified HS/LS MOSFET-based multi-channel power stages (6 channels, 1 kHz–20 kHz), and closed FEV and physical reliability issues (antenna, diodes, routing buffers) prior to tapeout.

AMSAnalog Circuit DesignAnalog CircuitsCadence VirtuosoCircuit DesignDesign+4

Intel corporation

AMS Design Engineer

Apr 2024 – May 2025 · 1 yr 1 mo · Bengalure · On-site

Worked on Intel 7nm, 5nm, and 18A nodes for UCIe high-speed interconnect IP, supporting AMS verification, characterization, and reliability sign-off.
Led Dot-libs characterization, extracting timing parameters, validating clock collaterals, and ensuring simulation-to-silicon correlation across PVT corners.
Performed AMS co-simulations using behavioral models, validating analog–digital interactions, clocking integrity, and timing alignment.
Executed Formal Equivalence Verification (FEV) and Schematic vs Layout (SVL) checks within the SCAM flow, ensuring consistency across abstraction levels.
Verified multiple blocks across 6 Gbps / 8 Gbps operating modes.
Conducted extensive PVT, Thermal, EOS, HEV, Nova, and Aged Nova reliability analyses (–40°C to 150°C, 1500 samples).
Performed PV, ICCT, RV, EM, and IR analyses; resolved layout-level stress issues for sign-off closure.
Enabled scalable CBB porting through disciplined hierarchical verification and documentation.

AMSAnalog Circuit DesignAnalog CircuitsCadence VirtuosoCircuit DesignDesign

Silicon labs

AMS Verification Engineer

Mar 2023 – Apr 2024 · 1 yr 1 mo · Hyderabad, Telangana, India · Hybrid

Worked on AMS verification - Verified behavioural models across analog–digital boundaries to ensure functional accuracy.
Performed co-simulations (Cosims) to validate interactions between RTL and AMS components.
Analyzed corner cases, timing alignment, and signal integrity across mixed-signal interfaces.
Ensured model correlation and stability to support reliable system-level verification.

AMSAnalog Circuit DesignAnalog CircuitsCadence VirtuosoCircuit Design

Wipro

Design Researcher ER&D

Aug 2022 – Jul 2025 · 2 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Worked on AMS Verification for Multiple IPs.
Turnkey Solution for SOCs.
Analog Design for HSIOs , GPIOs
FEV - Dot-lib Characterisation

SiliconAMSAnalog Circuit DesignAnalog CircuitsCadence VirtuosoFEV+1

Nxp semiconductors

Analog Design Engineer

Aug 2022 – Feb 2023 · 6 mos · Bengaluru, Karnataka, India · Hybrid

Analog Verification of Security Encrypted IP . Worked on Functional and Schematic Mode of Regression Analysis with wreal models .

Analog CircuitsSiliconAnalog Circuit DesignDesign Verification TestingMixed-Signal IC Design

Hcl engineering and r&d services

2 roles

Member Of Technical Staff - IO Developement

Jul 2021 – Aug 2022 · 1 yr 1 mo · Kolkata, West Bengal, India

LDOVerilog-AMSSiliconAnalog Circuit DesignLinuxCadence

IO Developement Intern

Nov 2020 – Jul 2021 · 8 mos · Kolkata, West Bengal, India

Project Name - Design of LVCMOS GPIO 45 nm
Project Description - Have worked in designing the Transmitter (Tx) of a GPIO ( General Purpose Input Output ) Block in 45 nm Technology Node via Cadence Virtuoso .
The Blocks being developed by me were :
1) Driver ( Pull Up Driver and Pull Down Driver )
2) Pre Drivers ( The Pre Drivers required the implementation of Break Before Make Technology to reduce the crowbar current affecting the Leakage Power when the input seems to be switching between 2 defined levels )
3) Logic Block for the Pre Driver ( Having the Z state )
4) The Level Up Shifter Block ( For switching between the VDDIO Level and the VDD level (for inputs coming from the the core intending to flow to the external world via the IO ))
5) Weak Pull Up and Pull Down Block which will help in defining the logic at a particular level and never keep the output of the Pad floating when the Tx is off .
Have performed the Performance Simulations in accordance to the data sheet and have successfully evaluated and bought the results ( Necessarily the DC Specs consisting of the Drive Strength IOH and IOL and the Transient Specs within range ) . Used ADEXL for simulating all the schematics. Did Monte Carlo Sampling over 1500 samples .
PVT range varied across tt,sf,fs,ss,ff : 0.9-1.1V : -40:25:140•C Corners .
CAD Tools Used - Cadence Virtuoso
Technology Node - 45 nm Technology Node .