Shidu G — Director of Engineering

• Expert in “netlist to GDS” implementation of SOC designs and Intellectual Properties(IP's) (includes Floor-planning, Clock tree synthesis, place and route, static timing analysis, signal integrity analysis/repair, extraction, physical verification DRC/LVS, IR drop analysis etc). Proficient in both synopsys and cadence EDA tools • Experienced in leading methodology development teams and developing physical design flows for nanometer process technologies. • Expert in generating and validating library views (LEF, FRAM, TIM, celtic view etc). • Experienced in RTL synthesis of IP's & low-power implementation. • Skilled in layout editing/generation and SSN spice simulation. Proficient in cadence virtuoso & synopsys HSPICE • Skilled in creating Perl and Tcl scripts for design automation. • Proficient in creating documents and schedules in MS Office suite & Frame-Maker. Specialties: • Extensive experience in designing/implementing Microprocessors, Basebands and Application processors. • Adept at interacting with vendors, creating design flows, and integrating IP’s and SOC’s. • An effective communicator, skilled in interviewing top candidates for key positions and creating a productive and cohesive team environment.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SOC and ASIC development.

Location: Bengaluru, Karnataka, India

Experience: 20 yrs 5 mos