Jan 2015 – Sep 2016 · 1 yr 8 mos · Bangalore

• GFAST Giga DSL Chipset CPE/CO SOC Design,Integration, IP design and macro delivery.

Sep 2011 – Aug 2014 · 2 yrs 11 mos · Bengaluru, Karnataka, India

• Redstone Digital macro(Cortex M0 based Power management IC) Delivery,Team lead handled MicroArchitecture,RTL design,Unit level testing,technical support and guidance for offsite consultant engineers responsible for the macro delivery.
• Marconi High Performance Analog RF IC FPGA prototyping.Complete ASIC porting ,planning and guidance,feasibility study of FPGA board selection.Successfully ported,prototyped and tested high gate count logic for software functionality on board leading to successful ASIC tapeout.
• MICA Platform(Cortex M0+ based SOC) and DRV12X (Cortex M0 based Motor Drive IC),» Liable for Integration stage approval of Cortex M0 centered subsystem design.Responsible for test plan growth, coverage research and analyze case development.SOC integration testing involving memories,bus interface standards and SOC components executed successfully.

Oct 2003 – Aug 2011 · 7 yrs 10 mos · Bengaluru, Karnataka, India

• Handled the SIO4-2D macro digital design,integration,synthesis,DFT and verification.
• RFID-TSENSE (Temp sensor) using RFID) ,handled entire design flow activities synthesis,STA,formal verification,DFT,ATPG and FPGA board level testing.
• Data Converter Macro implementation ,handled entire design flow activities synthesis,STA,formal verification,DFT and ATPG.
• SPC3 (SPMI Controller),Verification team lead handled verification of the SPC3 core,introduced system verilog verification methodologies into the company's verification flow.Implemented
• checkers,test bench, and wrote test cases for SPMI compliancy checking.
• ECF (Energy Controller for FPGA),Developed RTL for FPGA Xilinx and Altera technologies,ported RTL to numerous FPGA boards for research,development and demonstrating the Automatic voltage scaling technology in FPGA.External Customer support done for ECF customers.
• LM0505 (Energy Management Unit for DVS with I2C interface),Handled RTL design,Created unit level and System level test benches in Systemverilog.Handled the complete design flow processes such as Synthesis,STA,DFT,ATPG,Formality and Interaction with Physical design engineers for tapeout closure.Wrote the complete set of test cases for the LM0505

Jul 2001 – Sep 2003 · 2 yrs 2 mos · San Jose Bay area,California,USA

• Created top level Microarchitecture of the SDIO controller core
• Managed a team of 8 engineers in US and India through the Design, validation and board testing phase of the SDIO core
• Created custom SDIO controller architecture for integration of SDIO core with UART and DMA interface
• Did extensive Interaction with customers in explaining the technical features and capabilities of the SDIO Core and handle technical presentations of the core to potential customers
• Ported SDIO/SD logic to Altera and Xilinx platforms for protoyping and technical demonstration.

Oct 2000 – Jun 2001 · 8 mos · San Jose Bay area,California,USA

• SOC integration testing of the Infineon Tricore processor based 32X DVD Raptor chip using IKOS Hardware Accelerator/Simulator.
• Wrote system level test cases in C to test memory interfaces and AFE interfaces of the Infineon Tricore processor based 32X DVD Raptor chip.
• Responsible for generating production test patterns for the chip (DVD) using Infineon’s in house pattern generator tools.
• Verified the gate level netlist using Ikos hardware accelerator / simulator,debug & fix SOC integration issues & regress.

Jan 2000 – Sep 2000 · 8 mos · Sunnyvale,California area, USA

• RTL integration & Verification of multiple UART chip modul on a single die.
• Glue logic implementation and integration for single die configurable PC UART.
• Implemented FIFO architecture for 4 channel UART device
• Functional Verification of the design in 450,550, 650 and 750 modes of UART operation.
• Pre-layout Gate level verification of the device.

Jul 1998 – Dec 1999 · 1 yr 5 mos · Dupont,Washington area,USA

• Worked on the design ,development and support of Bus Interface Unit Module in the Merced (Itanium), Williamette and P6 processor.
• Model support engineer-XTG (modeling) group providing Engineering support for Intel BFM's.

Jan 1998 – Jun 1998 · 5 mos · San Jose Bay area,California, USA

• Involved in the logic porting of voice data and signalling transmitter and receiver core onto a Xilinx FPGA core on an HSM2113 mother board.
• Involved in the design of a T1 SF and T1 ESF state machine module to handle signaling information from the AS2000 back plane to the Verilink HSM2113v daughter board.
• Generated test patterns,Gate level testing and debug done for the XAQTI XMAC (1000 Mbps Gigabit Ethernet Controller)

Apr 1997 – Dec 1997 · 8 mos · Dupont,Washington area,USA

• Design and Validate components of Graphics Expander Bridge for the 82460GX chipset
• Designed the CORE in the GXB module of the 82460GX PCI chip set
• Implemented the behavioral model of the GXB CORE module in VHDL.
• Involved in the design of the bus interface unit in the graphics expander bridge for the 82460GX PCI chip set (GART and AGP bus arbiter) based on the AGP (Accelerated Graphics Port) specification
• Responsible for the System level and unit level verification of the GXB unit.

Oct 1996 – Mar 1997 · 5 mos · Greater Chennai Area

• Client : Cypress and Sapien Designs
• Designed and Validated USB 1.1 function controller.
• Developed a behavioral USB hub controller model.
• Architecture definition of USB 1.1 function controller.
• RTL design using VHDL & Verilog,creating synthesize able USB 1.1 cores.
• Targeted FPGA technologies of Altera and Actel families for porting the USB 1.1 core.
• Designed endpoint controllers,arbitrators,CRC generators and FIFO's for the USB 1.1 core.
• Responsible for the compliant checklist testing of the USB 1.1 core.

Sep 1995 – May 1996 · 8 mos · Gujarat,India

• Undergone training in the field of electronic circuitry design of Programmable Logic Controller based automation machines.
• Undergone training in usage of programming techniques for control of servo motors in CNC machines such as ARROG, ARROR and FAG mig 510,these robotic machines were used in manufacturing of precise metal parts for the bearing industry.
• Worked on Contactor logic based machines.