S

Sindhu Valleturi

CEO

Bangalore Rural, Karnataka, India0 mo experience

Key Highlights

  • Master's degree in Electrical and Electronics Engineering.
  • Strong foundation in formal verification and logic synthesis.
  • Excellent communication skills for technical collaboration.
Stackforce AI infers this person is a candidate with a strong background in Electrical Engineering and digital design methodologies.

Contact

sindhuvalleturi7@gmail.comLinkedIn

Skills

Other Skills

Formal VerificationLogic SynthesisStatic Timing AnalysisCommunication

Education

Quba College of Engineering & Technology

Master's degree — Electrical and Electronics Engineering

Apr 2017 – Feb 2019

Priyadarshini college of Engineering And Technology, Nellore

Bachelor's degree — Electrical and Electronics Engineering

May 2008 – Jun 2013

Stackforce found 100+ more professionals with Formal Verification & Logic Synthesis

Explore similar profiles based on matching skills and experience

ABHINANDAN .

ABHINANDAN .

Analog Design Engineer (External)

at Synopsys Inc

Una, India2 yrs exp
Analog Circuit Design
Sreekanth Billupati

Sreekanth Billupati

Digital Design Engineer

at C2i Semiconductors

Sri Potti Sriramulu Nellore, India6 yrs 11 mos exp
Product Design5G New Radio (NR)Team Leadership
Varun Kumar

Varun Kumar

Synthesis/STA Engineer (Contractor)

at AMD

Hyderabad, India1 yr 1 mo exp
Integrated Circuit DesignPhysical Design
Ankur Kumar

Ankur Kumar

Senior Flight Software Enginner

at Pixxel

Bengaluru, India5 yrs 6 mos exp
Embedded LinuxFPGA DesignRTL DesignVerification and ValidationSubject Matter Expertise
Basannagouda Reddy

Basannagouda Reddy

Director R&D

at Synopsys Inc

San Francisco, United States23 yrs 2 mos exp
Venkata Durga Prabhas Allacheruvu

Venkata Durga Prabhas Allacheruvu

ASIC Design Verification Engineer SpanIdea Systems @ Broadcom

at SpanIdea Systems

Guntur, India1 yr 11 mos exp
ASIC / SoC VerificationUVMVerification and Validation (V&V)
Vijayalaxmi Raddiyavar

Vijayalaxmi Raddiyavar

SRAM library validation

at Intel

Bengaluru, India4 yrs 6 mos exp
SRAMLibrary ValidationComponent DesignPDK ValidationSimulation
Jeevan Kishore Challa

Jeevan Kishore Challa

Senior Physical Design Engineer

at Qualcomm

Hyderabad, India5 yrs 7 mos exp
Physical DesignTeaching