Nov 2024 – Jan 2025 · 2 mos · Bengaluru, Karnataka, India · Hybrid

• Responsibilities:
• > Lead post-silicon validation for Xeon and Node (Xeon +AI Accelerator) in the Data Center market as part of the AISV India team.
• > Develop test plans implement to have directed and random test cases, drive functional coverage closure for validation & Bringup of Intel AI Hardware System of Xeon and Gaudi AI accelerator.

May 2023 – Nov 2024 · 1 yr 6 mos · Bengaluru, Karnataka, India · Hybrid

• Responsibilities:
• > Develop validation test plans for Boot and Reset flow validation of Intel Xeon Server Processors SoC by assessing delta of next generation processors.
• > Lead debug and drive root-cause analysis for SoC related issues in Boot and Reset flows.
• > Collaborate with cross-functional teams in developing tools to improve SoC validation and debug.
• > Drive technical enhancement for post-silicon validation infrastructure [Software (OS/BIOS/FW), Hardware(DIMM,PCIE/CXL cards), Automation environment, and Lab setup]
• > Manage and track technical issues, risks and priorities. Manage executive communications, including program status, risks and opportunities.
• > Provide Technical insights on volume validation execution reports and highlight key issues to program management.

Feb 2021 – May 2023 · 2 yrs 3 mos · Bengaluru, Karnataka, India · Hybrid

• As a System Validation/Post-silicon Validation engineer I will work with team members to drive execution towards tape-in quality power-on readiness and post silicon validation for all Reset flows, functional power management features. I will be working in a cross functional team to develop validation and debug strategies for post-silicon coverage, including shift left pre-silicon efforts to work with virtual platform simulation, FPGA emulation, and real hardware to ensure the devices meet our customer specifications and use cases.
• > Drive execution towards tape-in quality power-on readiness and post silicon validation.
• > Silicon level HW architectural validation and accountable to find design implementation bugs through Post SI system level validation.
• > Creates, defines, and develops system validation environment and test suites.
• > Responsible for the development of methodologies, execution of validation plans, and debug of failures.
• > Understands System with HW/FW/SW components as a whole, drives test execution and debug with cross functional teams.
• > Define validation requirement, access mechanism board requirement and test logic required to achieve validation coverage.
• > Involved in validation plan document writeup, test content development, test content pre-silicon emulation, test content post silicon bring-up bench related debug.

May 2019 – Feb 2021 · 1 yr 9 mos · Bengaluru Area, India

• Responsibilities:
• > Bring up expertise and first level support to SW/FW teams during bring up.
• > Developing C based tests and executing these on Virtual Platform/emulation platforms.
• > Understanding the intricacies of the CPU micro-architecture and defining how to push the test boundaries.
• > Architect and develop solutions to improve the generation of stimuli to produce programs to stress next generation CPU’s.
• >Drive validation strategy, build test plans for module/SOC validation.
• > Experience in validating SOC ARM CPUs, Cache Coherency, Power management, Security, Boot/Reset, Trace & Debug flows.
• > Solid understanding of system and processor architecture, and the interaction of computer hardware with software
• > Understanding of software and/or hardware validation techniques.
• > Knowledge on Debug Tools for JTAG, on chip trace features and ability to debug.

Jan 2016 – May 2019 · 3 yrs 4 mos

• Senior Staff Hardware Engineer at IBM India Systems and Technology Lab (ISDL) in Server Processor Development team.
• Responsibilities:
• > Perform Pre and Post silicon System BringUp
• > Developing sequence for lab debug and error collection
• > Supporting team in fail debug and analysis

Jul 2012 – Dec 2015 · 3 yrs 5 mos

• Associate Hardware Engineer at IBM India Systems and Technology Lab (ISTL) in Server Processor Development team.
• Responsibilities:
• > Perform fullchip pre-silicon BringUp verification using HW Emulator and post-silicon bring up debug & support
• > Perform System functional verification Testing and Debug
• > Perform System Bring Up/Integration
• > Apply Error Inject Methodologies
• > Analyze and solve technical problems/issues and provide/suggest solutions that can be implemented in a timely matter
• > Develop verification environment and architect test generators for block and system level test environment

Sep 2011 – May 2012 · 8 mos · Banglore

• Completed my final year project of M.Tech (VLSI) as Technical Intern at IBM India Systems and Technology Lab (ISTL) in Server Processor Development team.
• Project Title: Verification methodology for Interrupt Structure and Auto Power On Reset (POR) sequence in a Multi-Core Processor
• This work is devoted for the design of verification methodology for Interrupt structure and Auto POR (Power On Reset) in a multi-core processor. All units in a processor have common error reporting components to form a hierarchical reporting tree. The POR (Power On Reset) sequence is used to initialize the chip within this system and starts the cores. During this work the cycle based simulation is implemented to verify the interrupt structure and Auto POR of a multi-core processor

May 2011 – Aug 2011 · 3 mos · Pune Area, India

• I am assigned to help my co-students in cadence tool Flow and to debug the problems. Help them with Design/Tool support and maintain lab