Srinivasan T — Software Engineer
I’m a Senior Staff R&D Engineer at Synopsys with 8+ years of experience in developing and leading Verification IP (VIP) solutions for complex, high-speed protocols. I specialize in SystemVerilog and UVM-based VIP development, owning end-to-end delivery—from specification analysis and architecture to feature implementation, coverage closure, customer integration, and post-release support. Over the years, I’ve taken complete ownership of multiple protocols including UFS, SoundWire, RFFE, and SPMI, acting as the primary technical interface for customers and internal stakeholders. My role naturally evolved into a technical-lead capacity, mentoring engineers, planning deliverables, tracking execution, and ensuring high-quality releases. I’ve been recognized with multiple Customer Delight, Shining Star, Individual Excellence, and Team Awards, and actively contribute to industry standards through MIPI working groups (UniPro 3.0, M-PHY 6.0).
Stackforce AI infers this person is a highly skilled Verification IP Engineer in the semiconductor industry.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 7 mos
Skills
- Verification Ip
- Systemverilog
- Ufs
- Rffe
- Spmi
- Soundwire
- Gddr6
- Hbm
Career Highlights
- 8+ years in Verification IP development.
- Led multiple high-speed protocol projects.
- Recognized with multiple excellence awards.
Work Experience
Synopsys Inc
R&D Sr Staff Engineer (1 mo)
R&D Staff Engineer (2 yrs 2 mos)
R&D Engineer Sr II (1 mo)
R&D Engineer Sr I (2 yrs 5 mos)
R&D Engineer II (1 yr 6 mos)
R&D Engineer I (1 yr 1 mo)
SmartDV Technologies India Private Limited
ASIC Verification Engineer (1 yr 4 mos)
Education
Bachelor of Engineering - BE at Kongu Engineering College