Sep 2021 – Dec 2025 · 4 yrs 3 mos · Bengaluru, Karnataka, India · On-site

• Synth flow development.

Jul 2018 – Aug 2021 · 3 yrs 1 mo · Austin, Texas Metropolitan Area · On-site

• EMIR flow development.

May 2017 – Apr 2018 · 11 mos · Austin, Texas Metropolitan Area

• EMIR flow development.
• Designed a tile-based algorithm to perform analysis on larger designs in parallel without affecting the accuracy of the analysis.
• Developed various features such as exhaustive vectorless scan-capture analysis for user-defined “N-bit scan type”, grading runs based on a set of specific error & warning messages and extraction of results.
• Developed a web-dashboard in python to populate the results in a meaningful manner.
• Developed interactive python notebooks to visualize the combined tiled results (VDD, VSS, & loop resistance) using jupyter notebooks, datashader & bokeh libraries.

May 2016 – Aug 2016 · 3 mos · Bengaluru, Karnataka, India

• Module design & implementation, and debug for Snapdragon Display Engine (SDE).
• Ensuring design quality through Lint, CDC, and power-domain-crossing (UPF) checks.
• Estimating the power consumption at the early RTL stage to identify and optimize the design for low-power.
• Performing PPA activities to reduce area and power.
• Constraining and synthesizing the design for better QoR (low-area, high-speed, low-congestion, and low-power).
• Formal verification (and ECO) on the final netlist vs. RTL.
• Qualifying the final netlist through STA, PTPX, and VLP/CLP checks.
• Assisting verification team and other cross-functional teams for quick closure of issues.
• Creating scripts to extract and populate the reports from various tools

Jun 2013 – Apr 2016 · 2 yrs 10 mos · Bengaluru, Karnataka, India

• Module design & implementation, and debug for Snapdragon Display Engine (SDE).
• Ensuring design quality through Lint, CDC, and power-domain-crossing (UPF) checks.
• Estimating the power consumption at the early RTL stage to identify and optimize the design for low-power.
• Constraining and synthesizing the design for better QoR (low-area, high-speed, low-congestion, and low-power).
• Formal verification (and ECO) on the final netlist vs. RTL.
• Qualifying the final netlist through STA, PTPX, and VLP/CLP checks.
• Assisting verification team and other cross-functional teams for quick closure of issues.
• Creating scripts to extract and populate the reports from various tools