S

Sunjiv Sachan

Director of Engineering

Bengaluru, Karnataka, India31 yrs 2 mos experience

Highly Stable

Key Highlights

30 years of experience in DFT and design.
Led DFx COE team at Intel.
Proven track record in design and architecture.

Stackforce AI infers this person is a seasoned expert in semiconductor design and testing, specializing in DFT and SoC architectures.

Contact

Skills

Core Skills

DftDesign For Test

Other Skills

micro-architectureArchitectureSystem on a Chip (SoC)Design for DebugDesign For Debug

About

Bachelors in Electronics and Communication, IIT Roorkee, India. 30 years of Industry Experience in Design, Scan/ATPG, Design For Test (DFT) and Design For Debug (DFD). Led DFx for multiple successful Tape outs. Proven track record at design, micro-arch and architecture. Built DFx COE team from scratch and led them to own independent charter in Intel.

Experience

31 yrs 2 mos

Total Experience

4 yrs 5 mos

Average Tenure

3 mos

Current Experience

Semifive

Senior Director - DFT

Mar 2026 – Present · 3 mos · Bengaluru · On-site

Cisco

Principal Hardware Engineer - DFT

Feb 2024 – Mar 2026 · 2 yrs 1 mo · Bengaluru, Karnataka, India · On-site

Defined DFT Architecture and leading DFT implementation from start to silicon bring up

DFTDesign For Test

Intel corporation

2 roles

DFx Principal Engineer

Promoted

Mar 2017 – Jan 2024 · 6 yrs 10 mos · Bengaluru, Karnataka, India · On-site

micro-architectureArchitectureSystem on a Chip (SoC)DFTDesign For TestDesign for Debug

DFT Tech Lead

Sep 2005 – Feb 2017 · 11 yrs 5 mos · Bengaluru, Karnataka, India · On-site

System on a Chip (SoC)DFT

Pmc-sierra is now microsemi

DFT Senior Engineer

Jan 2001 – May 2005 · 4 yrs 4 mos · United States · On-site

System on a Chip (SoC)DFT

Lattice semiconductor

Design Engineer

Sep 1998 – Jan 2001 · 2 yrs 4 mos · United States · On-site

Duet technologies

Member of Technical Staff

Mar 1998 – Sep 1998 · 6 mos · United States · On-site

System on a Chip (SoC)

Stmicroelectronics

Design Engineer

Jun 1995 – Dec 1997 · 2 yrs 6 mos · India · On-site

System on a Chip (SoC)DFT

Associated electronics research foundation

Design Engineer

Jul 1994 – Jun 1995 · 11 mos · India · On-site

Education

Indian Institute of Technology, Roorkee

Bachelor of Engineering - BE — Electronics and Communication

May 1990 – May 1994

Stackforce found 100+ more professionals with Dft & Design For Test

Explore similar profiles based on matching skills and experience

Devesh Prajapat

Analog Circuit Design Engineer II

at Cadence

Bikaner, India3 yrs 4 mos exp

Mixed-Signal IC DesignAnalog Integrated Circuit DesignDigital Circuit Design

Subrata Roy

Director

at NVIDIA

Bengaluru, India25 yrs 1 mo exp

EDADFTC++HDLFPGA

Pradeep Korada

Associate

at PwC India

Srikakulam, India3 yrs 9 mos exp

Embedded SystemsFirmware

S Thimothy

Software Engineer

at HCLTech

Hubli-Dharwad, India1 yr 3 mos exp

Design AutomationVLSISilicon ValidationHardware EngineeringRTL Design

Nilam Sachan

Senior Manager R&D

at Synopsys Inc

Noida, India22 yrs 10 mos exp

Product DevelopmentProject ManagementArchitectural DesignDFTTechnical Leadership

Shivani Kapoor

RTL Design Engineer

at NVIDIA

San Francisco, United States8 yrs 2 mos exp

RTL DesignComputer ArchitectureTeam LeadershipDigital IC DesignSoC Design

Suryashankar Dasgupta

Senior Field Application Engineer

at NXP Semiconductors

Bengaluru, India8 yrs 9 mos exp

AUTOSAREmbedded SystemsBSW

Manjunatha Belagundi

Product Owner

at Capgemini

Bengaluru, India12 yrs 11 mos exp

Product ManagementSolution ArchitectureEmbedded SystemsAUTOSAREmbedded Software Development