Surendra Lodhi

Software Engineer

Bengaluru, Karnataka, India6 yrs 7 mos experience

Highly Stable

Key Highlights

6+ years in VLSI Design Flow and quality checks.
Expertise in TCL scripting for timing analysis.
Handled multiple SOC partitions from synthesis to sign-off.

Stackforce AI infers this person is a VLSI Design Engineer with extensive experience in semiconductor design and quality assurance.

Contact

Skills

Core Skills

Static Timing AnalysisPhysical DesignTiming Analysis

Other Skills

PrimePowerSynthesisPrimetime Quality Check ToolFloorplanPlacementComputer ArchitectureMicro architectureDigital ElectronicsVery-Large-Scale Integration (VLSI)Image ProcessingVerilogMatlabPythonMicrosoft OfficeC (Programming Language)

About

I am having 6+ years of experience in solution-oriented VLSI Design Flow, have handled multiple partitions simultaneously from synthesis till the sign-off process. Also, have been accountable for maneuvering primetime quality check tool for SOC. Along with possessing practical expertise in scripting TCL for timing, have also performed caliber fixes for primetime quality check tool. Have explicit work experience in Computer Architecture.

Experience

6 yrs 7 mos

Total Experience

2 yrs 9 mos

Average Tenure

1 yr 2 mos

Current Experience

Qualcomm

Senior Lead Engineer

Apr 2025 – Present · 1 yr 2 mos · Bengaluru, Karnataka, India

Mediatek

2 roles

Staff Engineer

Jun 2024 – May 2025 · 11 mos · Bengaluru, Karnataka, India

Senior Engineer

Apr 2022 – Jun 2024 · 2 yrs 2 mos · Bengaluru, Karnataka, India

Static Timing AnalysisPrimePower

Blaize

Design Engineer II

Jan 2022 – Apr 2022 · 3 mos · Hyderabad, Telangana, India

I am handing power optimisation in PnR flow

Hcl technologies

Physical Design Engineer

Aug 2019 – Jan 2022 · 2 yrs 5 mos · Bangalore

Physical Design Engineer (ST Microelecronics)
Roles & Responsibilities
Handled flat model SOC from Synthesis till PnR.
Did IORing and macro placement at floorplan stage.
Congestion and timing fixes at placement.
Multisource CTS building, Fixing high clock ID issues, Htree implementation.
STA Engineer (Intel Technology)
Roles & Responsibilities
Handled primetime quality check tool for SOC (Intel Project).
ResponsibleforgivingallfixesforprimetimequalityviolationstoSubsystem’s&PartitionOwner’s. • Effectively gave feedback to all the Subsystem and Partition Owner’s effectively.
Physical Design Engineer (Intel Technology)
Roles & Responsibilities
Worked on 4 partitions simultaneously for Intel Project, including PnR flow and all the side flow’s. • Closed timing for 17 timing corners for 10 nm methodologies and frequency upto 1.39 Ghz.
Fixing timing and congestion issues in placement stage using path grouping and bound creation. • Worked on post route drc analysis and given the effective feedback to the signoff team.
Good Understanding of Timing Analysis at block level, DRVs like max trans, max cap & slowslope.
CPU Design Debugging Engineer Oct 2019 - Mar 2020 • Debugged different type of bugs ex KOS, MPMM, Store Mismatch, RIP Mismatch.
Resolved the AMD Micro-Architecture bugs (i.e. related to FE, DE, EX & LSDC units).
Have good understanding of 64 bit computer architecture and AMD micro architecture.
ORCATOP training project
Worked on ORCATOP ASIC physical design flows and methodologies in 28 nm and frequency upto 428 Mhz.
Performed floorplan and placement for macro manually based on flyline analysis.