Jan 2025 – Jun 2025 · 5 mos · Sas Nagar, Punjab, India · On-site

• I have a strong foundation in digital design and VLSI testing, with focused exposure to Design-for-Testability (DFT) methodologies through practical lab work and independent projects. During my internship at Semiconductor Laboratory (SCL), Mohali under MeitY and ISRO, I gained hands-on experience in real GaN wafer and MEMS device testing, operating advanced semiconductor equipment like the Cascade Summit 12K probe station. Alongside this, I was introduced to and trained on DFT workflows, including concepts of scan chain design, Automatic Test Pattern Generation (ATPG), Memory BIST (MBIST), boundary scan, test coverage analysis, and fault models such as stuck-at and bridging faults, all within a real wafer-level testing and validation environment.
• To complement this, I’m currently working on a DFT-oriented Scan-Based ALU project in Verilog, where I’m integrating scan D flip-flops into an ALU design and simulating stuck-at faults within the scan chains. Fault detection and test validation are performed through scan mode simulation in QuestaSim, aligning with standard DFT validation techniques. Additionally, I have completed projects involving RTL module designs (SPI, I2C protocols, FSM controllers), including implementation and testing on an Artix-7 FPGA board and simulation using Vivado and QuestaSim. My certifications in VLSI Testing, Chip Design, and Semiconductor Fabrication further reinforce my understanding of DFT principles and SoC testability integration.

Jun 2024 – Jul 2024 · 1 mo · Remote · Remote

• VLSI Design Intern – CodTech IT Solutions
• June 1, 2024 – July 30, 2024
• Designed RTL components and FSM-based architectures using Verilog, focusing on modular, synthesizable designs.
• Developed and verified Finite State Machines (FSMs) for applications such as traffic light controllers, showcasing state transitions and timing accuracy.
• Created a synchronous FIFO with read/write logic, full/empty flags, and buffer control, applying UVM for functional verification.
• Designed and simulated SPI and I2C communication protocols, implementing configurable clock modes and address matching.
• Synthesized and validated multiple IP blocks using Xilinx Vivado and simulated functional behavior with QuestaSim.

Feb 2024 – Apr 2024 · 2 mos · Remote · Remote

• Embedded Systems Intern – Emertex
• February 9, 2024 – April 18, 2024
• Gained hands-on experience in embedded system design using ESP32 and PIC microcontrollers.
• Worked on sensor-based embedded applications, integrating real-time control systems with IoT interfaces.
• Programmed devices using Embedded C and tools like Arduino IDE, MPLAB IDE, and PICSim Lab.
• Developed an automated mopping robot using ESP8266 with dual control modes (manual & autonomous), awarded 2nd place at Yuva Utsav Science Fair.
• Built a gyroscope-controlled smart car using ESP32 and mobile web server, enabling real-time directional control over Wi-Fi.
• Simulated a washing machine control system using timers, state machines, and user feedback features.