Vinay Vasista

Software Engineer

Bangalore, Karnataka, India12 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in Compiler Optimization and Performance Tuning.
Innovative algorithm developer for retail automation.
Strong background in High Performance Computing.

Stackforce AI infers this person is a Backend-heavy Fullstack Engineer specializing in Compiler Optimization and Performance Tuning.

Contact

vvasista@d-matrix.ai LinkedIn

Skills

Core Skills

Compiler OptimizationPerformance OptimizationAlgorithm Development

Other Skills

Code GenerationVerilogVHDLCycleSimClusteringPartitioningUnion-FindPessimism ReductionOrder Fulfillment AutomationTrip GenerationAlgorithmsHigh Performance ComputingParallel ComputingData StructuresCache Optimizations

About

Experienced Software Engineer with a demonstrated history of working in the computer software industry. Skilled in C, C++, Python, OpenMP, Performance Tuning, and Compiler Optimization. Strong engineering professional with a Master of Science (M.Sc.) focused in Parallel and High Performance Computing from Indian Institute of Science.

Experience

12 yrs 7 mos

Total Experience

2 yrs 8 mos

Average Tenure

1 yr 9 mos

Current Experience

D-matrix

Senior Staff Engineer

Sep 2024 – Present · 1 yr 9 mos · Mysuru, Karnataka, India · Hybrid

Intel corporation

Deep Learning Compiler Engineer

Feb 2019 – Sep 2024 · 5 yrs 7 mos · Bengaluru, Karnataka, India · Remote

Worked on Compiler codegen and optimization for Habana AI Accelerators.

Compiler OptimizationCode Generation

Mentor graphics

Lead Member Of Technical Staff

May 2017 – Feb 2019 · 1 yr 9 mos · Bengaluru, Karnataka, India

Worked on Electronic Design Automation (EDA), particularly on performance optimization in Verilog, VHDL software simulation; Built CycleSim prototype simulator; Efficient clustering and partitioning of Processor circuit designs to leverage simulation parallelism; Implemented customized Union-Find structures to improve compile-time of clustering, on designs with million+ gates; Implemented Pessimism Reduction in logic gates with unknown inputs to improve determinism;

Performance OptimizationVerilogVHDLCycleSimClusteringPartitioning+2

@walmartlabs india

Software Engineer

Aug 2016 – Apr 2017 · 8 mos · Bengaluru, Karnataka, India

Worked with Order Fulfillment automation team on Trip Generation product. This product intended at generating trips for human and/or robot pickers inside Walmart Distribution Centers (DCs). Implemented various kinds of profiles, that provide stateful information to the logic of many automated fulfillment processes.
In addition to this, I came up with an innovative Algorithm to improve the existing Pick Sequencing algorithm, and built a working prototype. The objective was to optimize the distance traveled by the Picker during Order Fulfillment. With this, every Picker's productivity improves by spending more time in picking items and less time in walking/movement, there by improving the DC's efficiency.

Order Fulfillment AutomationAlgorithm DevelopmentTrip Generation

Indian institute of science (iisc)

2 roles

Research Associate

Feb 2016 – Jul 2016 · 5 mos

Teaching Assistant

Aug 2013 – Jan 2016 · 2 yrs 5 mos

Research on performance optimization, adding compiler optimization support, programming and analyzing faster Image Processing application programs, Lattice-Boltzmann Model programs, Multigrid Numerical Method programs on Multicore architectures, leveraging parallelism and cache utilization.