Vishal Manikwar

Software Engineer

Hyderabad, Telangana, India12 yrs 9 mos experience

Key Highlights

  • Expert in ASIC design verification and VLSI.
  • Proficient in SystemVerilog and UVM methodologies.
  • Strong background in SoC verification and IP integration.
Stackforce AI infers this person is a VLSI and ASIC design verification specialist.

Contact

LinkedIn

Skills

Other Skills

VLSICSystemVerilogVerilog HDLDigital Logic DesignDigital ElectronicsVerilogIP VerificationIP Integration & Verification at SoCUniversal Verification Methodology (UVM)

Experience

12 yrs 9 mos
Total Experience
5 yrs 2 mos
Average Tenure
2 yrs 4 mos
Current Experience

Amd

MTS Silicon Design Engineer

Jan 2024 – Present · 2 yrs 4 mos · Hyderabad, Telangana, India · On-site

Micron technology

Staff Engineer - Asic Design Verification

Aug 2021 – Jan 2024 · 2 yrs 5 mos · Hyderabad, Telangana, India

  • SoC Verification

Amd

3 roles

Sr Silicon Design Engineer

Promoted

Jul 2018 – Jul 2021 · 3 yrs

  • IP level verification, IP integration and verification at SoC.

Design Engineer 2

Promoted

Jul 2014 – Jul 2018 · 4 yrs

Design Engineer 1

Jul 2013 – Jul 2014 · 1 yr

Education

National Institute of Technology, Tiruchirappalli

Master of Technology (M.Tech.)

Jan 2011 – Jan 2013

Shri Guru Gobind Singh Institute of Engineering & Technology, Nanded, Maharashtra, India.

Bachelor’s Degree — Electronics and Telecommunication Engineering

Jan 2006 – Jan 2010

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