Vivek Kumar Rai

CTO

Bengaluru, Karnataka, India14 yrs 2 mos experience

Key Highlights

Expert in Verification and Validation for ASIC design.
Proficient in multiple hardware description languages.
Strong leadership experience in digital design engineering.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC design and validation.

Contact

Skills

Core Skills

Verification And Validation (v&v)Application-specific Integrated Circuits (asic)

Other Skills

VerilogC++Static Timing AnalysisDesign & VerificationPerlSystem VerilogAssertionsUVMAnalog LayoutOVMFunctional Verification

Experience

14 yrs 2 mos

Total Experience

1 yr 10 mos

Average Tenure

1 yr 1 mo

Current Experience

Google

DV Lead

May 2025 – Present · 1 yr 1 mo · Bengaluru, Karnataka, India · Hybrid

Analog devices

Staff Engineer

Mar 2023 – May 2025 · 2 yrs 2 mos · Bengaluru, Karnataka, India · Hybrid

VerilogVerification and Validation (V&V)Application-Specific Integrated Circuits (ASIC)

Intel corporation

Sr. Pre-Silicon Verification Engineer

Jun 2022 – Apr 2023 · 10 mos · Bengaluru, Karnataka, India · Hybrid

VerilogVerification and Validation (V&V)Application-Specific Integrated Circuits (ASIC)

Qualcomm

Sr. Lead Engineer

Nov 2019 – Jun 2022 · 2 yrs 7 mos · Bengaluru, Karnataka, India

VerilogVerification and Validation (V&V)Application-Specific Integrated Circuits (ASIC)

Texas instruments

Digital Design Engineer

Jul 2018 – Nov 2019 · 1 yr 4 mos · Bengaluru, Karnataka, India

VerilogVerification and Validation (V&V)Application-Specific Integrated Circuits (ASIC)

Nxp semiconductors

2 roles

Design Engineer II Lead

Apr 2018 – Jul 2018 · 3 mos · Noida Area, India

VerilogVerification and Validation (V&V)Application-Specific Integrated Circuits (ASIC)

Senior Design Engineer

Nov 2016 – Mar 2018 · 1 yr 4 mos · Noida Area, India

VerilogVerification and Validation (V&V)Application-Specific Integrated Circuits (ASIC)

Aricent

Senior Engineer

Oct 2015 – Oct 2016 · 1 yr · Bangalore

VerilogVerification and Validation (V&V)Application-Specific Integrated Circuits (ASIC)

Wipro technologies

Project Engineer

Oct 2011 – Sep 2015 · 3 yrs 11 mos · Pune Area, India

VerilogVerification and Validation (V&V)

Education

Birla Institute of Technology and Science, Pilani

Master’s Degree — MICROELCTRONICS

DIT UNIVERSITY

Bachelor’s Degree — Electronics & Communication

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