Vyasa Maharshi Grandhi — CEO

Experience: 12 plus years in Architecture, Microarchitecture, and ASIC/SoC RTL Design and Integration. Extensive knowledge in ASIC/SOC design flow. • Hands on experience in Architecture, Micro-Architecture - SoC/Subsystem/IP Level. • Hands on experience and strong knowledge in SoC Design, SOC RTL Design and Integration. • Have extensive coding skills and hands on experience in writing Synthesizable RTL using Verilog/VHDL/System Verilog for IP Level/SS/SOC Level. • Have Extensive knowledge on processors and protocols like Intel CPU X86, RISC-V, ARM CPU Cortex-R52, Cortex-A53, Arm-GPU-Camera- ISP (Mali C71), GPU IP and ARM Interface/IP protocols (GIC, SMMU, ADB Bridges, AXI3, AXI4, AXI4Lite, AHB, APB), FlexNoc Generation, Cache Coherency Interconnect, GIC controllers, Low peripheral protocols (I2C, UART, SPI), Basic knowledge on PCIE and USB protocols. • Good knowledge and Experience in handling ARM based SoC complex Architectures of Automotive, communications, Networking and multimedia. • Good Knowledge in handling SoC PAD and GPIO logic. • Good knowledge and hands on in clock and reset management blocks. • Hands on experience in configure and generation of Complex NOC’s for SoC using ARM -Socrates (NIC 400) or Arteries - FlexNoc along with performance modelling simulations. • Hands on Experience in IPXACT creation and IPXACT based integration, Register IP creation/CSR Generation and IP RAL model generation using Magillem && Synopsys Core Tools. • Hands on experience in creating Flatten IPXACT Register xml of SoC with full address/Memory Map view for DV RAL model generation. • Hands on Experience in writing Synthesizable RTL Design using Verilog HDL for IP/SS/SoC level. • Hands on experience on Lint and CDC, Spyglass DFT, Spyglass LDRC checking’s on SoC level or Block Level or IP Level. • Have hands on experience in writing functional test cases for unit/IP/chip level and in analyzing the simulation dumps. • Hands on experience in writing Timing constraints Synopsys Design Constraints (SDC) and Static Timing Analysis. • Have extensive Knowledge on Low Power Design techniques and Implementation using UPF and Power checks and Analysis. • Hands on Knowledge on Synthesis and STA, and Flow knowledge of physical design flow from Floor Plan to GDSII • Basic knowledge on DFT design and its techniques. • Hands on Experience on Fixing Functional ECOs on pre and Post netlists using Synopsys Verdi and Conformal LEC or by writing tcl scripts for Synopsys DC and ICC. • knowledge on FPGA design and prototyping.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in SoC architecture and RTL development.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs 8 mos