Yug Raheja — Product Engineer

As a pre-final year Electronics student at MAIT Delhi, I’m passionate about digital design, RTL development, and the VLSI design flow. I enjoy working with Verilog and exploring the full hardware development cycle—from logic design to simulation and synthesis. My recent exposure at DRDO-SSPL has strengthened my understanding. I'm particularly interested in ASIC and FPGA design, low-power digital systems, and hardware-software co-design. With a strong foundation in digital electronics and continuous hands-on learning, I aim to contribute to cutting-edge VLSI innovations that powers real-world technology.

Stackforce AI infers this person is a VLSI design enthusiast with a focus on digital electronics and hardware development.

Location: New Delhi, Delhi, India

Experience: 2 yrs 7 mos