Keshav Gupta

Software Engineer

New York, New York, United States7 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in FPGA development with a focus on hardware engineering.
Experience in real-time data processing and encryption technologies.
Strong background in statistical analysis and predictive modeling.

Stackforce AI infers this person is a Hardware Engineer specializing in FPGA development and real-time processing for telecommunications and finance.

Contact

Skills

Core Skills

Fpga DevelopmentHardware EngineeringData Science

Other Skills

AndroidBloggingC++Computer HardwareComputer NetworkingComputer SoftwareData PredictionElectronicsEncryptionEthernet CommunicationHardware AccelerationHigh-Level SynthesisJavaScriptLaTeXProgramming

About

Currently an FPGA Engineer at Citadel Securities. l've completed my bachelors (S.B.), masters (M.Eng.) and Engineer's (ENG) in Electrical Engineering and Computer Science from MIT. Previously worked as a hardware verification intern at NVIDIA (Summer 2019) and Microsoft (Summer 2020), worked on applying Robust Synthetic Control to Cricket Score Prediction at MIT LIDS and worked with MIT App Inventor Group at CSAIL on loT with App Inventor. I took some university level online courses while in high school, related to my field of interest, through edX (mainly Microsoft, MITx, and IITBombayX). Volunteering as a Community TA gave me an opportunity to help fellow online learners. I am also a huge cricket fan, and have been an integral part of the MIT Cricket Club!

Experience

Citadel securities

FPGA Engineer

Sep 2025 – Present · 6 mos · New York, United States · On-site

Massachusetts institute of technology

4 roles

Teaching Assistant for Computation Structures

Sep 2024 – May 2025 · 8 mos · Cambridge, Massachusetts, United States · On-site

Teaching Assistant for Computation Structures

Feb 2023 – Jun 2023 · 4 mos · On-site

Worked as a TA for the MIT class 6.004/6.1910: Computation Structures.

Research Assistant

Jun 2021 – Jun 2023 · 2 yrs · On-site

Teaching Assistant for Digital Systems Lab

Aug 2020 – Jan 2021 · 5 mos · Cambridge, Massachusetts, United States

Teaching Assistant for MIT Course 6.111: Introduction to Digital Systems Laboratory

Iragecapital advisory private limited

FPGA Engineer

Jun 2023 – Aug 2024 · 1 yr 2 mos · Mumbai, Maharashtra, India · Hybrid

Worked as an FPGA developer for the HFT tech stack.
Recent projects include:
In-house MAC/PCS core for reduced latency in 10GbE Ethernet communication.
HLS toolchain for reduced strategy-to-live time.
Realtime, zero-latency AES encryption core for encryption of outgoing orders to NSE, BSE and MCX.

FPGA DevelopmentHardware Engineering

Mit research laboratory of electronics

Research Assistant

Jan 2021 – Jun 2023 · 2 yrs 5 mos · Cambridge, Massachusetts, United States

Research Assistant at MIT LEAN, working on hardware accelerators for autonomous exploration.

Microsoft

Hardware Verification Intern

Jun 2020 – Aug 2020 · 2 mos · Sunnyvale, California, United States

Massachusetts institute of technology

Lab Assistant for Microcomputer Project Lab

Feb 2020 – May 2020 · 3 mos · Greater Boston

Mit research laboratory of electronics

SuperUROP Researcher at MIT RLE

Aug 2019 – May 2020 · 9 mos · Greater Boston

Worked on a hardware accelerator for realtime Shannon Mutual Information computation for fast autonomous exploration.

Nvidia

ASIC Verification Intern

Jun 2019 – Aug 2019 · 2 mos · San Francisco Bay Area

Massachusetts institute of technology

Lab Assistant for Circuits and Electronics

Sep 2018 – May 2019 · 8 mos · Greater Boston

Mit lids

UROP Researcher at LIDS (Laboratory for Information and Decision Systems)

May 2018 – Dec 2018 · 7 mos · Greater Boston

Cricket games are often interrupted due to rainy conditions. In such cases, Duckworth-Lewis-Stern method is the agreed upon approach to declare the winner. This project finds an application of Robust Synthetic Control to score and result prediction in these cases.