Anushka Singh Raghuvanshi — Software Engineer

As VLSI designer with a passion for digital design and verification, I am dedicated to developing innovative solutions that meet the demands of the ever-changing technology industry. My technical proficiency includes C Programming, Cadence Virtuoso, Static Timing Analysis, Verilog, and Vivado - Xilinx. With experience in implementing a 5-stage pipelined RISC processor, designing parameterized synchronous FIFO, implementing sequence detector, and developing wireless vineyard monitoring systems, I am confident in my ability to tackle complex design challenges. During my time as a RTL Design and Verification Trainee at Maven Silicon, I have learned testbench components in SystemVerilog and UVM along with verification of the design. As a teaching assistant for Digital Design at BITS Pilani, I was responsible for invigilating lab exams and correcting answer sheets. These experiences have honed my communication and teamwork skills, and I am excited to continue to develop these skills in my future endeavors. One of my most notable projects involved designing a 5-stage pipelined RISC processor in Verilog HDL using Xilinx Vivado tool. The processor includes forwarding which resolves data hazards and supports R-type, I-type, and J-type instructions. Another project involved designing a floating-point adder (IEEE 754 floating-point single-precision 32-bit format) in Verilog HDL using Xilinx Vivado tool. In addition to my technical skills, I have also achieved academic success, earning a 95.91 percentile in my subjects/electives which include Digital Design, VLSI Architectures, VLSI Design, FSM based design, RTL Coding, and Protocols (UART, I2C, SPI). I am excited to continue to explore the possibilities of digital design and verification and to contribute to the growth and success of the technology industry.

Stackforce AI infers this person is a VLSI design specialist with a focus on digital design and verification.

Location: Hyderabad, Telangana, India

Experience: 1 yr 8 mos