Abhishek Verma

Product Engineer

Bengaluru, Karnataka, India1 yr 5 mos experience
Most Likely To SwitchAI ML Practitioner

Key Highlights

  • Expert in RTL Design and Digital IC Design.
  • Experience in high-speed communication protocols and ML acceleration.
  • Proficient in FPGA development for AI workloads.
Stackforce AI infers this person is a VLSI and FPGA specialist with a focus on AI hardware solutions.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignDigital Ic DesignFpga

Other Skills

AI workloadAnalog Circuit DesignAnalog SemiconductorsArduinoAssembly LanguageC (Programming Language)CMOSCircuitCircuit DesignClock Tree SynthesisDigital DesignsEDAElectronic CircuitsField-Programmable Gate Arrays (FPGA)Hardware development

Experience

Analog devices

Design Verification Engineer

Feb 2025 – Present · 1 yr 1 mo · Bengaluru, Karnataka, India · On-site

  • Working along SoC DV team, who is Designing-verifying SiP(4nm,5nm,16nm Libs) having high speed comm. protocol(UCIe), ADC-DAC, Processor Subsys, Compute block for Special Purpose + ML acceleration.
RTL DesignProblem SolvingKeysight EDA Advanced Design SystemDigital DesignsStatic Timing AnalysisTcl-Tk+27

Confidential

FPGA Developer- Internship

Sep 2024 – Jan 2025 · 4 mos · Surat, Gujarat, India · On-site

  • Worked on development team, making Efficient Hardware to tackle AI workload harnessing FPGA-CPU compute.
FPGAAI workloadHardware development

Education

Indian Institute of Technology, Roorkee

Master of Technology - MTech — Electrical Engineering

Jul 2022 – Jul 2024

JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA

Bachelor of Technology (B.Tech.) — Electrical and Electronics Engineering

Stackforce found 100+ more professionals with Rtl Design & Digital Ic Design

Explore similar profiles based on matching skills and experience

Neha Bajaj

Neha Bajaj

Power Management IP Architecture Lead

at Google

San Diego, United States19 yrs exp
MANDEEP SINGH

MANDEEP SINGH

Staff Engineer

at Qualcomm

Bengaluru, India8 yrs 10 mos exp
Venkatramana Gajavelli

Venkatramana Gajavelli

Staff Engineer

at Qualcomm

Hyderabad, India11 yrs 8 mos exp
DDR Protocols
Aneek Jash

Aneek Jash

Circuit Design Engineer

at Intel Corporation

Bengaluru, India2 yrs 7 mos exp
Dynamic SimulationStandard Cell Design
Pramathesh Trivedi

Pramathesh Trivedi

Staff Engineer

at Qualcomm

Bengaluru, India8 yrs 10 mos exp
Fabric DevelopmentDesign for debug (DFD)
Nonie Politi

Nonie Politi

FPGA Developer

at Hudson River Trading

Singapore, Singapore16 yrs 5 mos exp
Digital Circuit DesignEmbedded Systems DesignFPGA DevelopmentResearch and Development
Shankar Prasad (Agrawal)

Shankar Prasad (Agrawal)

IP RTL Design

at NXP Semiconductors

Bengaluru, India9 yrs 8 mos exp
MicroarchitectureRTL CodingRTL DevelopmentSystem Architecture
Harshad Kulkarni

Harshad Kulkarni

Lead FPGA Design Engineer

at Baker Hughes

Pune, India9 yrs 6 mos exp