Shubham Anand

CTO

Bengaluru, Karnataka, India5 yrs 9 mos experience

Highly Stable

Key Highlights

Over 6 years of experience in formal verification.
Expert in low power design and verification methodologies.
Strong scripting skills in Perl and TCL for automation.

Stackforce AI infers this person is a semiconductor verification engineer with expertise in formal verification and low-power design.

Contact

anandshubham.0561@gmail.com LinkedIn

Skills

Core Skills

Formal VerificationLow-power Design

Other Skills

ECOUnified Power Format (UPF)VC LPPhysical DesignVerilogShell ScriptingGraphicsApplication-Specific Integrated Circuits (ASIC)System on a Chip (SoC)PerlLeadershipCommunicationDigital IC Designsystem verilogTCL

About

I am senior lead engineer at Qualcomm with over 6 years of experience of driving Formal Equivalence Verification (FEV) signoff for multiple blocks. I have completed M.Tech in VLSI designs from VIT Chennai, and have developed a strong skill set in FEV, functional ECOs and low power verification concepts with the use of eda tools such as Cadence Conformal LEC and Formality. I am also well-versed in scripting languages such as Perl and TCL. Additionally, I have a basic understanding of HDLs like Verilog and various physical design attributes. I am always looking to connect with professionals in the Vlsi design industry, and I am eager to expand my network and learn from others in the field. Connect with me to know more about my experience and skills.

Experience

5 yrs 9 mos

Total Experience

4 yrs 9 mos

Average Tenure

1 yr

Current Experience

Qualcomm

Senior Lead Engineer

May 2025 – Present · 1 yr · Bangalore Urban, Karnataka, India · On-site

ECOUnified Power Format (UPF)VC LPPhysical DesignFormal VerificationVerilog+25

Intel corporation

2 roles

GPU Physical Design Engineer

Aug 2020 – May 2025 · 4 yrs 9 mos · Bengaluru, Karnataka, India · Hybrid

> Works with implementation team in performing formal verification sign off for SOCs.
> Performs NEQ debug, abort resolution for multiple blocks.
>FEV flow updates for efficient memory usage and run times through some automations with the help of scripting languages like perl, TCL and Cshell
> Worked on generating functional ECO patches for implementing changes during the final phase of the projects.
> Executed LPFEV to address the low power issues in the design.

Conformal LECEquivalence CheckingFormal VerificationLow-power Design

Graduate Technical Intern

Jul 2019 – Jun 2020 · 11 mos · Banglore

> Worked with methodology team for resolving issues related to formal verification of integrated graphic chips by using tools like LEC and Formality.
> Performed quality checks over the new tool versions to ensure good run time and memory usage.
>Worked over Auto-ECO process through Lynx and did some small automation using scripting like perl, TCL and Cshell in the FV flow.
> Worked with the IP team on designs and helped in abort resolving, NEQs debug and recipe updates.
> Performed LPFEV and worked on debugging LPFEV failures.