R

Rushikesh Landge Patil

Software Engineer

Bengaluru, Karnataka, India2 yrs 8 mos experience

Key Highlights

  • 3+ years of experience in Physical Design Engineering.
  • Expertise in advanced technology nodes like 4nm and 3nm.
  • Proficient in timing analysis and physical verification.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design for advanced technology nodes.

Contact

LinkedIn

Skills

Core Skills

Very-large-scale Integration (vlsi)

Other Skills

Application-Specific Integrated Circuits (ASIC)Digital IC DesignLow Power IC designPhysical DesignRTL DesignCadence VirtuosoInnovusXilinx ISEGenusPython (Programming Language)TCLVerilog

About

Physical Design Engineer with 3+ years of experience. Complete ownership of Block from Floorplan to Signoff on advanced technology nodes(4nm, 3nm). Timing analysis, Congestion, IR Analysis, Physical Verification.

Experience

2 yrs 8 mos
Total Experience
1 yr 11 mos
Average Tenure
9 mos
Current Experience

Syntiant corp.

Physical Design Engineer

Jul 2025 – Present · 9 mos · Bengaluru, Karnataka, India

Mediatek

Physical Design Engineer (Direct Contract)

Aug 2023 – Jul 2025 · 1 yr 11 mos · Bengaluru, Karnataka, India

Apex semiconductor

Physical Design Intern

Sep 2022 – May 2023 · 8 mos · Bengaluru, Karnataka, India

Very-Large-Scale Integration (VLSI)

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI design

Jan 2021 – Jan 2023

MIT World Peace University

Bachelor of Technology - BTech — Electronics and communication engineering

Jun 2017 – May 2021

Stackforce found 100+ more professionals with Very-large-scale Integration (vlsi)

Explore similar profiles based on matching skills and experience

Amit R

Amit R

Senior Synthesis ( C/T)

at MediaTek

Bengaluru, India8 yrs 4 mos exp
Physical DesignStatic Timing Analysis
PK

Pradeep Kumar

Senior Physical Design Engineer

at Qualcomm

Noida, India7 yrs 8 mos exp
Physical Design engineerPNR
Ashok Kumar

Ashok Kumar

Senior Lead Engineer

at Qualcomm

Bengaluru, India8 yrs 5 mos exp
pavan kumar jangam

pavan kumar jangam

Sr Design Engineer

at AMD

Chennai, India6 yrs 5 mos exp
EngineeringDesign
DA

Dheeraj Anand

Senior Manager Silicon Design Engineering

at AMD

Bengaluru, India20 yrs 5 mos exp
VLSIPhysical Design
Anuruth S

Anuruth S

Accumulated Expertise

at Career-Wide Experience

Karur, India0 mo exp
SK

Susee KSP

Technical Recruiter

at Semi-leaf consulting firm

Bengaluru, India5 yrs 4 mos exp
HiringNiche Talent Acquisition
Arun Kumar

Arun Kumar

Verification Engineer

at Alpha Numero (ANTS Global Systems Pvt Ltd)

Ahmedabad, India3 yrs 3 mos exp
DO-254 processFunctional Verification