Aditya Panwar

CEO

Champaign, Illinois, United States4 yrs 3 mos experience

AI ML PractitionerAI Enabled

Key Highlights

Expert in hardware emulation and C++ development.
Designed Ethernet solutions for pre-silicon verification.
Passionate about advancing semiconductor technology.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in hardware design and emulation.

Contact

Skills

Core Skills

Hardware EmulationC++Analog Circuit DesignRtl Coding

Other Skills

ASIC VerificationAlgorithmsArduinoBashCPU designCacheCadence InnovusCadence VirtuosoComputer ArchitectureComputer HardwareConcurrent ProgrammingData StructuresDebuggingDesign Rule Checking (DRC)Digital Electronics

About

I’m a Master’s student in Electrical and Computer Engineering at UIUC, graduating in May 2026, with a focus on computer architecture, hardware design, and emulation. 🚀 I’m currently exploring: Co-op roles for Spring 2026 and Full-time opportunities post-graduation (May 2026) At Siemens EDA (Mentor Graphics), I worked as a Lead Member of Technical Staff, developing Ethernet-based virtual pre-silicon verification solutions for the emulation market. I initially joined as a Member of Technical Staff in 2021 after earning my B.E. in Electronics and Communication from NSIT. These experiences have deepened my interest in the intersection of hardware and software, particularly in processor microarchitecture, memory systems, and networking. I am passionate about electronics and innovation, and I enjoy working with a talented and diverse team of engineers. My goal is to contribute to the advancement of the semiconductor/EDA technology and deliver high-quality solutions.

Experience

Siemens eda (siemens digital industries software)

3 roles

Lead Member of Technical Staff

Dec 2024 – Jan 2025 · 1 mo

Designed emulation-friendly Ethernet Transactor IPs (VNA/VTL) supporting 1G–800G interfaces for pre-silicon verification of networking SoCs
Contributed to solution architecture, RTL design and verification, C++ software and DPI layer development
Gained expertise in emulation methodologies and tools, with hands-on experience on the Veloce emulation platform
Pioneered emulation performance improvements for Veloce CS platforms

EthernetSystemVerilogHardware EmulationC++PthreadsTechnical Project Leadership

Senior Member of Technical Staff

Promoted

Dec 2022 – Dec 2024 · 2 yrs

Member of Technical Staff

Jul 2021 – Dec 2022 · 1 yr 5 mos

Working on the development of the Ethernet transactor to create a virtual pre-silicon verification solution, as a part of the Veloce Transactors team.